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- Mon Sep 07, 2020 2:48 pm
- Forum: FV-1 hardware questions
- Topic: Would varying the clock input mess with the PLL?
- Replies: 1
- Views: 5099
Would varying the clock input mess with the PLL?
I'm another one who is attempting to implement an I2C slave in a microcontroller to emulate an external EEPROM. Mine is an ATSAMD21 from Atmel / Microchip. Just like others from that brand of microcontrollers, the on-board I2C slave wants to pause the SCL clock line to give the micro software enough...