Spin Semiconductor

Ah, that clarifies it, thank you. I'm guessing that applies to CHO RDA and CHO SOF, but CHO RDAL simply gives the live value all the time regardless?

Hi Frank, I'm trying to figure out when the CHO instructions stop using the internal register (REG flag) and revert to using the "live" LFO value. Application note AN-0001 (page 4) shows that once the REG flag is used, several subsequent CHO instructions continue to use the captured LFO va...

Thank you gentlemen
The latest download SpinSetup_1_1_31.exe (Ver 1.1.31.0) works.

Upon further investigation it seems that the compiler (at least my version of it: 1.0.1.2 - 13/11/2007) doesn't encode the JAM lfo number correctly. It encodes 53h for lfo 2 (RMP0) and encodes 73h for lfo 3 (RMP1), and it only accepts values 2 and 3 as valid. It should encode 2->93h and 3->D3h respe...

I'm trying to figure out what value JAM makes the ramp LFO restart at (high or low), and if it differs between forward ramp to reverse ramp. I wrote the following code to test both ways using POT0 to set the ramp direction, but the ramp doesn't seem to "jam"... skp RUN, START wldr 1, 0, 40...

Does the SKP instruction affect PACC? Or is it only ACC-changing functions that affect PACC?

I just want to clarify a conflict in the application Note AN-0001 regarding SINx_RATE. On page 4 at the bottom it states that "Kf(decimal) = Kf/512", but then on page 5 paragraph 3 it says "Kf(decimal) = (125/511) to (500/511)..." implying that Kf(decimal) = Kf/511. Page 4's form...

I'm trying to understand how the FV-1 allpass filter (RDA & WRAP) translates to an analog allpass filter and vice-versa. For an analog allpass (first-order): 90-degree phase shift happens at fc = 1/(2piRC). Does the RDA/WRAP coef (kap/-kap) relate to fc in the same way as it does with RDFX: fc =...

My question is about the down-counter address offset used to effectively 'shift' samples through a memory buffer: The way I understand it, there is an address offset in the background which gets added to all read and write operations to SRAM, and automatically decrements for each sample cycle. Would...

Ahhhh....I understand. That makes perfect sense now. Sorry it took half a dozen posts & replies! Thanks for your patience.

Mike.

So for WLDS (Page 3)… Ka = 2 * buffersize And for WRAX (Page 5)… Ka(decimal) = buffersize/32768 Only problem is, when you use the formula on page 4/5 to convert Ka for WLDS to Ka(decimal) for WRAX you end up with... Ka / 32768 = Ka(decimal) Which gives... (2*buffersize)/32768 = buffersize/32768 ...

Great, that explains CHO RDAL for ramp thanks! However, you didn't really answer my question about the conflict in the app note... Page 3: setting via WLDS suggests Ka = 2 * buffersize (approx)... delay1 mem 8193 ;+/-4096 ... wlds SIN0, 5, 16384 ;2 x mem alloc Page 5: setting via WRAX to RMP0_RATE s...

Ahhhh....that explains the pot range problem all right! Thanks for clearing that up for me. As far as setting the ramp rate via RMP0_RATE...I'm more interested in what CHO RDAL returns for RMP0, which I assumed would have the same amplitude as what you would pass to RMP0_RATE? I'm also still confuse...

Thanks for clarifying...it is possible that my pot was responsible for this as I use 3.0V for my pot supplies instead of 3.3V, therefore my RAMP_RATE may have been 9% lower than what I was expecting. (Although having said that, REFP is also fed 3.0V so I would have thought they would scale fully). M...

Hi Frank, I'm new to FV-1 and loving the capabilities! However, there is a piece of info I seem to be having trouble finding or wrapping my head around, and it's to do with the correlation between WLDR freq coef and RMP0_RATE freq (fractional) value. You can set up ramp speed using WLDR with a binar...