Search found 86 matches
- Thu Jun 12, 2025 3:24 pm
- Forum: Algorithm development
- Topic: CHO RDAL output range
- Replies: 3
- Views: 30259
Re: CHO RDAL output range
Im sorry that comment should have read "value + half ramp" or something unrelated to delay memory. I'm asking about the ramps in isolation. Not their relation to delay memory addresses. To rephrase I'm looking for the value ranges the CHO RDAL instruction adds to ACC. Are the ranges I list...
- Thu Jun 12, 2025 4:35 am
- Forum: Algorithm development
- Topic: CHO RDAL output range
- Replies: 3
- Views: 30259
CHO RDAL output range
According to the coding examples article: http://www.spinsemi.com/knowledge_base/coding_examples.html#Generating_triangle_waves skp run,1 ;establish LFO on first sample cycle only wldr rmp0,10,4096 ;set values for rate and range cho rdal,rmp0 ;read LFO saw wave, accumulator value will range from 0 t...
- Fri Jun 06, 2025 7:47 am
- Forum: Algorithm development
- Topic: MULX data resolution?
- Replies: 3
- Views: 19780
Re: MULX data resolution?
What instruction's coefficient are you referring to here? There's no coefficients for the MULX instruction.
- Fri Jun 06, 2025 2:03 am
- Forum: Algorithm development
- Topic: MULX data resolution?
- Replies: 3
- Views: 19780
MULX data resolution?
I have two positive counter with bipolar incrementation. The first one "A" works as intended while the other one "B" is stuck at 0Hz (no incrementation). The only difference in the codes is the value stored in 'base'. 1024 works fine while 256 does not. This seems to indicate tha...
- Wed May 28, 2025 1:54 am
- Forum: Algorithm development
- Topic: Delay memory interpolation (again)
- Replies: 8
- Views: 31823
Re: Delay memory interpolation (again)
Oh my. Thank you for this! Finally got this working. Here's a working code for anyone interested. You could probably filter the increment scaler pot for a smoother travel. equ scaler reg0 ; increment scaler POT equ counter reg1 ; pitch shift counter equ addr1 reg2 ; interpolation address 1 equ addr2...
- Mon May 26, 2025 12:59 pm
- Forum: Algorithm development
- Topic: Delay memory interpolation (again)
- Replies: 8
- Views: 31823
Re: Delay memory interpolation (again)
For some reason I've had the impression that an 8bit-resolution interpolator was baked into the ADDR_PTR / RMPA function. Seeing as there are 32768 buffer positions but the value inputted to the ADDR_PTR register has 32768*256 available values. I could have swore I read this but now re-reading throu...
- Mon May 26, 2025 11:49 am
- Forum: Algorithm development
- Topic: Delay memory interpolation (again)
- Replies: 8
- Views: 31823
Re: Delay memory interpolation (again)
It's not that I need more ramps it's that I find the RMP0/1 cumbersome to work with especially due to the specific buffer size options. If I could get the ADDR_PTR/RMPA approach working it's a much more flexible solution in my opinion. I very much think it is worthwhile as I have hundreds of FV1 chi...
- Mon May 26, 2025 8:16 am
- Forum: Algorithm development
- Topic: Delay memory interpolation (again)
- Replies: 8
- Views: 31823
Re: Delay memory interpolation (again)
The instruction is there to allow bipolar incrementation ("if GEZ : ACC = ACC-1) basically performing a rollover. I'm aware the fv1 uses 2s compliment for negative numbers but I don't see how that conflicts with this implementation. That being said the general method suffers from the same artif...
- Mon May 26, 2025 3:50 am
- Forum: Algorithm development
- Topic: Delay memory interpolation (again)
- Replies: 8
- Views: 31823
Delay memory interpolation (again)
I'm back at it attempting to increase the audio fidelity for non-ramp based delay interpolation (ADDR_PTR / RMPA). So far all my attempts seem to be in vain and I'm stuck wondering what exactly makes the SIN/RAMP LFO generated data sound so good and left wondering if there's more going on under the ...
- Wed Apr 09, 2025 9:23 am
- Forum: Algorithm development
- Topic: Language error for combining skip conditions?
- Replies: 3
- Views: 31976
Re: Language error for combining skip conditions?
Thank you! I wish that was stated in the reference manual. So creating an unconditional skip requires 2 instructions (given RUN is out of the question):
Code: Select all
skp gez, label
skp neg, label
label:- Wed Apr 09, 2025 2:31 am
- Forum: Algorithm development
- Topic: Language error for combining skip conditions?
- Replies: 3
- Views: 31976
Language error for combining skip conditions?
I'm having an issue with combining skip conditions. Setting the condition "NEG|GEZ" should result in a skip regardless of the value loaded into ACC. Similarly setting the condition "RUN" should yield the same result for every program cycle after the initial. I have a white noise ...
- Mon Jan 06, 2025 3:46 am
- Forum: Algorithm development
- Topic: Counter with bipolar incrementation
- Replies: 0
- Views: 51789
Counter with bipolar incrementation
I use a lot of counters in my projects but always found working with bipolar incrementation tricky. This is probably not news to more seasoned forum members but I thought I'd share my method here. Feel really dumb that I didn't think of this sooner. Feel free to critique/improve: This should work fo...
- Thu Jan 02, 2025 3:14 am
- Forum: FV-1 software questions
- Topic: Precision addition / RDAX scaler
- Replies: 5
- Views: 36699
Re: Precision addition / RDAX scaler
On mobile so cumbersome to do a complete check. I think the syntax is correct but most of the constants upper range limits are wrong in the cheat sheet. All the instructions expect EXP and SOF should have upper limits of 2-LSB not 1-LSB (S1.14 and S1.9).
- Wed Jan 01, 2025 4:00 am
- Forum: FV-1 hardware questions
- Topic: Pot Tracking Speed
- Replies: 18
- Views: 104519
Re:
I have been thinking about this issue for awhile, and I think I have a slick and simple solution to the pot speed issue. This should make a pot input usable for an expression pedal, for example. All that is needed is to counteract the action of the slow lowpass filter on the pot with a shelving hig...
- Mon Dec 23, 2024 10:36 am
- Forum: FV-1 software questions
- Topic: Precision addition / RDAX scaler
- Replies: 5
- Views: 36699
Re: Precision addition / RDAX scaler
Thank you! Will I be safe from rounding errors when using binary representation too? Btw note then that the info on the cheat sheet is incorrect regarding Rdax. I'd really appreciate an update of that page if possible as it is a very useful tool to me. If not a priority I could do an overview and wr...