Spin Semiconductor

I would recommend you start with Keith's notes on the spin site here . Then, if you have a technical book store near you (if in Los Angeles area check out OpAmp Technical books) then go and browse the books. I've found that which book works best for a person really varies. This is an online book tha...

Hi Tupelo, I cannot reproduce the error, below is my test code and a comment that may help: toggle equ reg0 skp run, start clr or 1 wrax toggle, 0 ; toggle = 1 ; start: ldax toggle ; load toggle skp zro, right; if toggle =0, output to right channel else left ; ldax adcl; read left input wrax dacl,0;...

They are pretty basic ADCs. They have some filtering and hysteresis in them to provide a stable value out. As this filtering and hystersis block is clocked it results in a 125mS time constant at 32KHz sample rate.

I would need to talk to Keith to get more detail on the circuit if you need it.

9-bit resolution on the POTS

While they are updated at Fs, there is some internal filtering of the pot causing it to have about a 100mS time constant.

Each POTX has it's own ADC, not multiplexed

Was thinking about it and I *think* that if you set the coefficient to the ramp in a pitch shift to less than -16384 (not allowed by the assembler however) the pointer would start to move backwards. Have not tried this but using the pitch transpose code and making the POT only go negative may demons...

Actually, you can use any input as a control signal. As the ADC and POTS are register mapped they can be read via RDAX, used as the coefficient in a MULX instruction, etc. So you should be able to read in an ADC input, find the amplitude of the signal and use it as a control function.

Actually, that seems like a very effective solution. The POT inputs are DC so a switch is just as valid as a pot and the POT input should go to a true 0 when shorted to ground.

You could try using a ramp and a CHO RDAL to read it into the accumulator and use it as the counter, will try to get a chance to try this later today.

The internal PLL generates an signal of 1024xFS and instruction rate is 128xFS.

Max sample rate should be about 50KHz. I have run chips beyond this but would not recommend it for production.

Hmmmm, not sure how to handle this in the FV-1. You could try using a counter and RMPA to read samples out in reverse but you will run off the end of the delay quickly and you will only get short burts of reverse audio I think. The FV-1 uses a down counter that is added to the address in instruction...

Matt is correct, if you look at the code the part that makes the ramp a triangle is:

cho rdal,rmp0 ;should range 0 to 0.5, a ramp
sof 1,-0.25 ;subtract 1/4 from the 0 to 1/2 result
absa ;make absolute; now 0 to 0.25

Hi Peter,

The 2-wire interface pins on the FV-1 use internal pull-ups so as long as the FV-1 is not accessing the EEPROM you should be able to read/write the EEPROM.

T1 is strictly for production test. It is designed to only be activated while the device is in the production tester.

Interesting question, I suppose you could look at the the LSBs of the ADC input or use them to seed an LFSR as saturation limiting is not applied to logical operations in the chip.

Sorry, there is no way to encrypt the programs in the external EEPROM.