Multiplier Block
Moderator: frank
Multiplier Block
I've been examining the FV-1 arithmetic processing architecture block diagram as depicted in SPINAsmUserManual.pdf (page 23), in that diagram I can see that the multiplier block takes inputs from the adder above it and from the LFO output or coefficients embedded in the instruction. I'm surprised that there is no data path going from the ACC (or PACC) back to the multiplier block. How does FV-1 actually implements multiplication of current accumulator value with the content of any given register (MULX operation)?
That diagram is a simplified drawing of the actual schematic. The purpose was to show how signals flow in the MAC/ALU and in what order (upper adder, multiplier, lower adder, etc.). It seems I missed something in the drawing but the data path is there since MULX does work 
The actual schematic is very complex as it has to account for sign extension, fp -> linear and linear -> fp conversion, etc. I couldn't put it in the docs and have it make sense to users.
The actual schematic is very complex as it has to account for sign extension, fp -> linear and linear -> fp conversion, etc. I couldn't put it in the docs and have it make sense to users.
Frank Thomson
Experimental Noize
Experimental Noize
Ah I see .
I was looking closely at this diagram because I'm unsure about MULX, the description about that instruction (http://www.spinsemi.com/knowledge_base/inst_syntax.html) says that "The upper 15 bits of the register are used as a coefficient, allowing a multiplier range of -1.0 to +0.999389". So the register content is actually truncated to 15 bits for the multiplication?
I'm doing a 2nd order (biquad) filter, and I thought that by storing the filter's coeffs in registers I would be able to preserve 24 bits coeffs, but if MULX truncates register content to 15 bits than I'd better off defining the coeffs as constants and use RDAX or SOF instruction instead. Is there any other way to keep 24 bits coeffs for filtering operation?
.I was looking closely at this diagram because I'm unsure about MULX, the description about that instruction (http://www.spinsemi.com/knowledge_base/inst_syntax.html) says that "The upper 15 bits of the register are used as a coefficient, allowing a multiplier range of -1.0 to +0.999389". So the register content is actually truncated to 15 bits for the multiplication?
I'm doing a 2nd order (biquad) filter, and I thought that by storing the filter's coeffs in registers I would be able to preserve 24 bits coeffs, but if MULX truncates register content to 15 bits than I'd better off defining the coeffs as constants and use RDAX or SOF instruction instead. Is there any other way to keep 24 bits coeffs for filtering operation?
Coefficients to the multiplier are limited to 15 or 16 bit, depends if there is an integer bit/where binary point is. The multiplicand is the full width so you can preserve data at 24-bit. For audio, 15 or 16 bit coefficients are fine for most applications.
As coefficients are always 15 or 16 bit there is no advantage to using an SOF or RDAX over a MULX, the coefficient will always be limited to that number of bits.
As coefficients are always 15 or 16 bit there is no advantage to using an SOF or RDAX over a MULX, the coefficient will always be limited to that number of bits.
Frank Thomson
Experimental Noize
Experimental Noize