Linearity of POTs

Hardware questions and issues with the FV-1

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rooster
Posts: 4
Joined: Thu Oct 11, 2012 1:55 am

Linearity of POTs

Post by rooster »

We are using FV-1 in measurement equipment, latest application is a swept bandpassfilter from 31.25 Hz to 8 kHz with exponential scale (equal octave steps), controlled with POT0.

While frequencies at the beginning, the end and in the middle (500 Hz and 1 kHz) are correct, the octaves 62.5 Hz and 4000 Hz show significant deviations. The pot used was a precision Potentiometer and the Voltage at the wiper was monitored. In order to eliminate any bugs in programming the filter, the pot0-output (0 to .99) was substituted with a corresponding fixed value x (SOF 0,x) in the range 0 to .99 and the frequencies were correct as expected.

So, a non linear output of POT0 referred to the control voltage (0 Volt to Ub) at the control pin for POT0 of the DSP was assumed.

To verify this, a simple volume control with POT0 was programmed.

; Test Programme. linear level control
; Author: Eberhard Hahn
; Pot0 is level

equ level reg1
rdax pot0,1 ;control (0 to .99...)
wrax level,0
rdax adcl,1 ; sample the left input
mulx level ; multiply with pot-output
wrax dacl,0 ; write left output

With an input of 100 mV the output was measured for several voltages at the contol pin for POT0. It showed that for control voltages up to approximately 130 mV, corresponding to nearly 4% of full scale (3.30V), no output appeared. Above this threshold, the output rose in steps of approximately 200 microvolt, which gives a resolution of nearly 10 bit. For the rest of the control voltage, the linearity was quite ok, except for the last 5%, where some saturation was found.

We would appreciate an explanation for this problem.
frank
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Joined: Wed Oct 19, 2005 12:26 pm
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Post by frank »

I believe what you are seeing is due to the way the ADC was implemented in the FV-1, it does not go fully rail to rail. The internals were designed to account for this so you still see the value go 0 to 0.99 in a program. You can probably just add resistors to each end of your POT so it matches the range of the FV-1 internally then the position should match the desired digital value.
Frank Thomson
Experimental Noize
rooster
Posts: 4
Joined: Thu Oct 11, 2012 1:55 am

Pots

Post by rooster »

Thank you, Frank, for the fast reply!

It is exactly what we supposed, that the ADC for the Pots does not go rail to rail. We alrady had the same idea which you suggested: providing resistors at both Pot-ends, so that the range is limited to 5% and 95% of UB. The linearity is excellent and the resolution (now approximately 9 bit) is more than sufficient!javascript:emoticon(':D')

Eberhard
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