adressing dely ram

[soulhammer]

hi to all,

i have some small problems understanding the addressing of the delay ram.

1) Calculating of RAM Addresses is done in the ACC and the registers, which are 24 bits wide. The addr_ptr as well as the address in the rda and wra instruction are 16bits wide. Which portion of the 24bits value is take for the addressing, the 16 lsb bits or the 16 msb bits?

2) My understanding of the delay ram is, that an "invisible" counter is decremented and determines the absolute read/write address of the delay ram cell. In the rda/wra instruction only a offset to this address counter is set. Is my understanding right? Is there any way to read the current pointer?

I'm currently trying to program a simple loop sampler using the the pot inputs for sample-start/playback-start and i am struggling around with the pointers for some days now with no clue for the right implementation

Thanks for any hint or help....

[frank]

1) Calculating of RAM Addresses is done in the ACC and the registers, which are 24 bits wide. The addr_ptr as well as the address in the rda and wra instruction are 16bits wide. Which portion of the 24bits value is take for the addressing, the 16 lsb bits or the 16 msb bits?

MSBs are used for addressing

2) My understanding of the delay ram is, that an "invisible" counter is decremented and determines the absolute read/write address of the delay ram cell. In the rda/wra instruction only a offset to this address counter is set. Is my understanding right? Is there any way to read the current pointer?

Your understanding is correct but there is no way to read the offset counter. You don't actually need to, just fill the buffer and when done filling read the tail, write it to the DAC then write it back to the head. You don't need to do any address calculations at all, just set up the buffer and read/write it.

I'm currently trying to program a simple loop sampler using the the pot inputs for sample-start/playback-start and i am struggling around with the pointers for some days now with no clue for the right implementation

I did a simple piece of code as an example of recording/playback, see http://www.spinsemi.com/forum/viewtopic.php?t=20

[soulhammer]

Hey Frank,

thanks for your quick an helpful reply. You gave me some hints to think about.
The implementation i planned, will provide an undefined loop lengths. The sample and playback loop length should be determined by independent external clock signals. The solution you provided uses the whole delay-ram depth as defined in the beginning of the routine and has so a fixed loop length. And to overcome this, will be the challenge

The hint regarding the MSBs was very helpful for me. I'll keep you informed regarding my progress. For now i start a second pointer (hopefully) running parallel to the delay-ram counter from which i calculated the pointer addresses for reading and writing....

As i said, i'll keep you informed

BTW, i'm working with the FV-1 development board for some weeks now (the development of first target hardware is nearly finished) and i must say, it makes lot of fun to program the chip and hear the results immediately. You made a great design with the chip as well with the assembler!!!
Just if i could express a wish for further chip releases, i would ask for more delay ram and some I/O pins for process steering. Just a wish...

[frank]

I don't think you will need to know the counter or even need to track it, the counter is always added so even when using addr_ptr the counter will be added. So as long as you know the starting address of a memory block you can add a value into it. For example:

mybuffer mem 16000

SpinAsm will define "mybuffer" with the starting address of the memory block so later you could do:

sof 0,0 ; clear ACC
or mybuffer ; load address of mybuffer into acc
rdax somereg,1.0 ; somereg has the offset into the buffer calculated earlier by some means and we now add it to the address of mybuffer

You will need to be careful of alignment as the OR I believe will LSB align so you will need to shift bits up before or after the add to properly access the memory.

[soulhammer]

Hi Frank,
thats what i tried before.
The problem is, that i get the sample at an undefined point in time, writes it into the buffer and now wants to read back exact this sample from memory at an other undefined point in time. For this i must know which offset i need to add to the starting address.

My understanding (from my small experience up to now with the chip) is, that the mybuffer constant points to the current delay ram counter and not to an absolute address. So when i read back, i need to know where the sample is placed in memory.

The delay ram implementation is excellent for chorus and delay applications. What i do is not really what the chip is designed for...

I found out a solution last night (after two bottles of beer) which works as expected. The essential information was about the MSBs for adressing you gave me yesterday.

I left away the reg declarations and the pot handling for a better overview. I guess the name of the registers speak for themselves.
The reg ram_ptr is decremented every sample and so runs simultaneously with the counter. From this i can calculate the absolute address and the offsets. For easier handling i copied the some constants into registers (lsb_reg=$000100 mem_depth_reg=$7ffe00)
The code isn't still finished, there are still some things to do to make it work perfect....
It looks a bit complicated and the handling of relative pointers not really belongs to the funny things i like to do in programming, but this was the only way i saw to implement it as desired. If anyone has an idea for an easier implementation, don't hesitate to post it...

Code: Select all

; -----------------------------------------------------------------------
; --- sample/playback ----
; -----------------------
; --- counter for absolute address ---
ldax ram_ptr		; decrement ram_ptr
rdax lsb_reg,-1		;
wrax ram_ptr,1
skp gez, END_DECREMENT
ldax mem_depth_reg
wrax ram_ptr,0		; reset ram_ptr

END_DECREMENT:

; -----------------------
; --- sampling ---- 
ldax sampleEdge		
skp neg, DO_SAMPLE	; starts on pos edge
clr
ldax ram_ptr
wrax write_addr_start,0	; store absolute adress of counter
sof 0, L			;
wrax sampleEdge,0	; reset sampleEdge

DO_SAMPLE:
ldax sampleState
skp neg, NO_SAMPLE	; sampling during H on pot1...
ldax ram_ptr		;
wrax write_addr_end,0	; contains absolute end pointer after sampling

ldax adcl			; load ADCL
;wrax dacl,1 		; write to output
wra ram_ptr,0 		; write sample to SRAM

NO_SAMPLE:

; -----------------------
; --- playback ---- 
ldax playbackEdge		
skp neg, DO_PLAYBACK	; starts on pos edge
sof 0, L			;
wrax playbackEdge,0	; reset playbackEdge
ldax write_addr_start	;
rdax ram_ptr,-1		; calculate pointer offset...
wrax read_addr_start,0	; ...and set read_addr_start pointer

DO_PLAYBACK:
ldax playbackState		; playback during H on pot2...
skp neg, END_PLAYBACK

clr
ldax read_addr_start
wrax addr_ptr,0
rmpa 1			; read out memory
wrax dacl,0 		; write to output

END_PLAYBACK:

; -----------------------------------------------------------------------

[Sweetalk]

It's really interesting! but, you're not limited by the FV-1 ram that gives you 1 sec of delay in 32768Hz Clock?, it's a little bit useless for a looper or record/playback effect. Or you're using a slower clock to have more delay lenght?

[Sweetalk]

It's really interesting! but, you're not limited by the FV-1 ram that gives you 1 sec of delay in 32768Hz Clock?, it's a little bit useless for a looper or record/playback effect. Or you're using a slower clock to have more delay lenght?

[soulhammer]

You're right. There is the limitation of 1s.
But as i offer this as only one program in a multieffect device for the modular synthesizer environment, there might be some people who likes to experiment with this. I'm yet not really clear what software will be implemented at the end. I let the customers decide...

BTW, this software has still some bugs...