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2 xFV-1 considerations ?

 
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ice-nine



Joined: 24 May 2012
Posts: 119

PostPosted: Thu May 15, 2014 10:34 am    Post subject: 2 xFV-1 considerations ? Reply with quote

I'm thinking of making a circuit which will use 2 FV-1 chips each with its own eeprom. The eeprom switching will be done using one selector so when for example program '0' is selected both FV-1's will receive there own (different) code from there respective Eeprom. The reason behind this is to allow for up to 6 dsp control pots and larger (in a way) program capability.

My questions are what should I consider in connecting the outputs of one FV-1 to the inputs of the second and will there be any timing problems running from separate crystals? (unlikelyi think) should both chips run from one crystal? Thirdly will there be any S/N ratio accumulation problem?
Thanks
Mick
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frank



Joined: 19 Oct 2005
Posts: 958

PostPosted: Thu May 15, 2014 1:14 pm    Post subject: Reply with quote

I haven't done this so these are thoughts just off the top of my head, if I miss something or am wrong about something I hope someone else catches it...

Use 1 crystal, there won't be any timing problems since it will be analog in and out but each FV-1 has a PLL, better if both see the same reference clock.

Converter noise will add when you run the out of one to the in of the other so if this is a mono device drive both ADC inputs and add the signals together in the FV-1. Signal should increase by about 6db but noise by only 3db. Also consider that it is delta-sigma converters so noise from the DAC is being pushed out of band and you don't want it to alias back in band in the ADC of the second FV-1 so a low pass filter between them is probably a must.
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Sweetalk



Joined: 15 Oct 2009
Posts: 95

PostPosted: Fri May 16, 2014 4:53 am    Post subject: Reply with quote

I'm starting a project with 2 FV-1's too for more control pots as well. So if I have some trouble or issue I'll post it!.
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ice-nine



Joined: 24 May 2012
Posts: 119

PostPosted: Fri May 16, 2014 7:23 am    Post subject: Reply with quote

Sweetalk wrote:
I'm starting a project with 2 FV-1's too for more control pots as well. So if I have some trouble or issue I'll post it!.


Thats great news Sweetalk, it's all thinking for me at the moment as I am off to the TT motorcycle races soon and will back June 17 so that wll be when any real layouts will start to happen for me.

I too will post any progress here.

Thanks Frank for the info also.
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GaryInThailand



Joined: 19 Sep 2014
Posts: 4
Location: Hua Hin, Thailand

PostPosted: Sat Oct 11, 2014 12:28 am    Post subject: Reply with quote

Any updates on this front? I'm about to configure 2 eval bds for series and parallel operation. I think that might be a bit of fun! Smile
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Sweetalk



Joined: 15 Oct 2009
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PostPosted: Mon Sep 28, 2015 6:17 am    Post subject: Reply with quote

In a different project I'm using 2 FV-1's but I must share control pots. It can be done with a single pot? (haven't tried yet, just evaluating possibilities but I don't want to use a dual pot). Thinked to buffer the CV signal and split it to both FV but the opamps offset will reduce the range of the pot. Any thoughs?.
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ice-nine



Joined: 24 May 2012
Posts: 119

PostPosted: Mon Sep 28, 2015 8:09 am    Post subject: Reply with quote

Sweetalk wrote:
In a different project I'm using 2 FV-1's but I must share control pots. It can be done with a single pot? (haven't tried yet, just evaluating possibilities but I don't want to use a dual pot). Thinked to buffer the CV signal and split it to both FV but the opamps offset will reduce the range of the pot. Any thoughs?.


From the datasheet
The input resistance of the potentiometer control inputs is on the order of 10 megohms, and these terminals are quite resistant to noise. No bypass capacitors should be required on these terminals. If not required, these terminals may be left open, or if the program includes the use of a potentiometer function, it may be connected to MID if a centered potentiometer position is desired, but an actual control is not intended in the design.

Reading this would suggest to me that you could use the wiper off one pot directly on multiple pot controls over the 2 FV-1's. Frank will be able to confirm or dismiss this.
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Sweetalk



Joined: 15 Oct 2009
Posts: 95

PostPosted: Mon Sep 28, 2015 9:18 am    Post subject: Reply with quote

ice-nine wrote:
Sweetalk wrote:
In a different project I'm using 2 FV-1's but I must share control pots. It can be done with a single pot? (haven't tried yet, just evaluating possibilities but I don't want to use a dual pot). Thinked to buffer the CV signal and split it to both FV but the opamps offset will reduce the range of the pot. Any thoughs?.


From the datasheet
The input resistance of the potentiometer control inputs is on the order of 10 megohms, and these terminals are quite resistant to noise. No bypass capacitors should be required on these terminals. If not required, these terminals may be left open, or if the program includes the use of a potentiometer function, it may be connected to MID if a centered potentiometer position is desired, but an actual control is not intended in the design.

Reading this would suggest to me that you could use the wiper off one pot directly on multiple pot controls over the 2 FV-1's. Frank will be able to confirm or dismiss this.


Looking in another topic Frank says that t'll be possible. You posted before me Razz
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tjm215



Joined: 22 Dec 2013
Posts: 17

PostPosted: Tue Dec 08, 2015 11:59 am    Post subject: Reply with quote

I was wondering if this would be an ok configuration for using two spins -

input buffer-->fv1A-->fv1B-->output buffer

would you need any buffering between the chips or is that not necessary?

also would i be able to drop the output resistor and capacitor of the first fv1 and the input resistor and capacitor on the second fv-1?
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frank



Joined: 19 Oct 2005
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PostPosted: Tue Dec 08, 2015 7:08 pm    Post subject: Reply with quote

I do not believe you would need buffering between the FV-1s but I would keep some filtering to remove out of band noise and any DC offset difference between the chips.
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