When I switch on power (after power has been off for over 10 seconds) I get
a big reverberated crash sound (presumably down to spike at ADC input).
I don't have that problem when switching to the program with the selector switches,
or if I power down and then quickly back on (say less than 1 second). It suggests
a problam with a capacitor somewhere (either near the regulator, or near the FV-1 input)
but I have had no luck fixing things in hardware.
So I am trying to fix this in software by muting the input for a second or so at start up.
Here's some test code showing the basic idea, which is to periodically increment
a register until it turns positive (indicating "mute period is over").
Code: Select all
mem delay 30000 ; To stage periodic increases to "level" register
equ level REG0 ; If "level" is negative ==> Muted
;-------------- Initialize -------------------
; To mute the input at start-up, we set the "level" register to -1.
; The delay line will periodically increase "level" until
; it turns positive, meaning "mute off".
skp run,end_init
sof 0,-1
wrax level,-0.34 ; Set "level" to -1
wra delay#,0 ; Write +0.34 to delay line output
end_init:
;-------------------------------------------------
;------------ Handle muting period ---------------
rdax level,1 ; Read level
skp gez,read_inputs ; If level >=0, jump to "read_inputs", else...
rda delay#,1
wrax level,1 ; .. increment level by output of delay line (i.e. either 0 or 0.34)
skp gez,read_inputs ; If level >= 0, jump to "read_inputs", else...
clr
rda delay#,1 ; ... read delay line output (Should be either 0 or 0.34)
wra delay,0 ; ... write to delay line input
skp zro,end_read_inputs ; Jump to "end_read_inputs"
;-------------------------------------------------
read_inputs:
rdax ADCL,0.5
rdax ADCR,0.5
end_read_inputs:
wrax DACL,1
wrax DACR,0
However if I power down for over 10 seconds and then power on, then it is permanently muted and
I never see an output.
That leads me to the conclusion that my assumption about delay memory being populated with
zeros at program start-up was not correct, and that the problematic power ups are somehow
leading to garbage in the delay memory. Is my understanding here correct, as I can not
think of another explanation?
Has anyone else experienced a problem with noise like this at power up and how was this fixed.
BTW, I am using a LDO regulator (LP2950_3.3) for the supply (which is 5.5V).