Help me understand the Delay SRAM and how to address it

Software questions and issues with the FV-1

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djd_oz
Posts: 1
Joined: Sun May 31, 2020 3:53 pm

Help me understand the Delay SRAM and how to address it

Post by djd_oz »

I understand that the Delay SRAM stores 32 kbits of samples which equates to 1 sec.

To write to the current /start of the Delay SRAM , we use the WRA instruction.

To read a sample from a particular location and output to ADCL, we do something like the below,

SOF 0,0
WRAX ADDR_PTR, 0

ADDR_PTR can be represented in either $8000 to $7FFF or -2 to 1.998...

or MEM which is 1 to 32768

Now, how do I read a sample for and what ADDR_PTR or ME- should I use for the following,

1) Current Sample - 1 Sample
2) Sample at 0.25 secs
3) Sample at 0.5 secs
4) Last sample in the Delay SRAM, i.e. 1 s

How does the FV-1 convert between integers, hex and float?

For example, I'm trying to undestand the below code for a 3 tap delay.

Code: Select all

RDAX ADCR,0.5000000000
MULX POT2
RDAX ADCL,1.0000000000
WRA 0,0.0
CLR
OR $007FFF00
MULX POT0
SOF 0.8074753571,0.0425292206
WRAX ADDR_PTR,0.0000000000
RMPA 1.0
WRAX REG0,0.0000000000
CLR
OR $007FFF00
MULX POT1
SOF 0.5699826050,0.0300296021
WRAX ADDR_PTR,0.0000000000
RMPA 1.0
WRAX REG1,0.0000000000
;------ Output
RDAX REG0,1.0000000000
WRAX DACL,0.0000000000
RDAX REG1,1.0000000000
WRAX DACR,0.0000000000

Based on the below coefficients, which delay sample will it be reading?

SOF 0.8074753571,0.0425292206
SOF 0.5699826050,0.0300296021
potul
Posts: 76
Joined: Tue Sep 26, 2017 12:33 am

Re: Help me understand the Delay SRAM and how to address it

Post by potul »

Hi,

My understanding is that ADDR_PTR is a 24 bits register, but to address the memory we don't really need that much. So the FV1 is using only the most significant bits of ADDR_PTR. This means that in fact memory addressing will go from 0 to 7FFF00 (note that 7FFF is 32767)
That's why you see the instruction "OR 7FFF00" and then multiply by the pot factor.

So 7FFF00 will be 1 second, and then you can do the math with the SOF instructions.

I guess that the offsets in the SOF instructions are there to avoid a Zero delay.

Mat
Digital Larry
Posts: 338
Joined: Mon Nov 12, 2012 1:12 pm
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Re: Help me understand the Delay SRAM and how to address it

Post by Digital Larry »

That code looks suspiciously like it was generated by SpinCAD.

Normally if you are using Spin ASM and using memory buffers, you will reference relative to the memory buffer, for example at the end, or in the middle (I forget the exact syntax). Or, the beginning of the buffer + 1, or 10, or whatever it is that you want.

SpinCAD doesn't do things this way because the memory assigned to a given block isn't represented the same way. I think it inherits the memory buffer model used by the ElmGen library upon which SpinCAD is based. So, in SpinCAD, memory references wind up with these bizarre scale/offset adjustments which, while they conceptually boil down to MEM + 10, or middle of MEM, or end of MEM, are really almost completely incomprehensible. Nobody would ever write SpinASM that way except for really unusual circumstances.

I suggest you study how memory buffers are used in SpinASM if your intention is to write things in SpinASM. Many of the supplied examples are further simplified by assuming that the memory buffer always starts at zero and/or uses the entire available memory.

DL
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