I'm having some trouble getting a smooth transition when using a momentary switch connected to a pot input to control pitch transposition.
The pitch transpose algorithm is just a modification of the familiar one and works fine (with a constant shift defined before the loop). The switching also works well but there is often an audible pop or click when it is engaged or disengaged. The switch pulls the pot high (with a pull down resistor for when it is off) and it is debounced with a standard RC circuit (with a resistor also in place to discharge the cap). I've played around with exaggerated debounce time constants and it hasn't improved the situation so I suspect it's an issue in the code.
I initially tried it with the switch reading code before the delay writes but then moved it to after them in case it was an issue with trying to perform the pitch processing on unpopulated delay lines, but it didn't make any noticeable difference.
Any help in identifying and remedying the problem would be much appreciated!
Ant
Code: Select all
LOOP:
rdax ADCL, 1.0 ;read left input
wra ldel, 0.0 ;write to delay --start
rdax ADCR, 1.0 ;read right input
wra rdel, 0.0 ;write to delay start
ldax pot0 ;load pot0 to acc
sof 1,-0.5 ;scale to -0.5 -> 0.5
skp NEG,SWOFF ;if acc -ve (switch is off) skip to SWOFF, else continue with pitch loop
clr
; We use the base of the sample memory block as the
; address since we are using a positive only ramp
; that ranges 0 to 1.0 (511 in this case)
;do left chan:
cho rda, rmp0,reg|compc,ldel ; (1-k)*sample[addr]
cho rda, rmp0,0,ldel+1 ; k*sample[addr+1] + ACC
wra dtemp, 0 ; Save it off to memory and clear ACC
cho rda, rmp0,rptr2|compc, ldel ; (1-k)*sample[addr+ half ramp]
cho rda, rmp0,rptr2,ldel+1 ; k*sample[addr+ half ramp + 1] + ACC
cho sof, rmp0,na|compc,0 ; Result in ACC, multiply it by (1-XFADE) coefficient
cho rda, rmp0,na,dtemp ; Add in earlier value saved in memory, multiply saved value by XFADE coefficient
wrax dacl, 0 ; Write it to DACL and clear ACC
;now do right chan:
cho rda, rmp0,compc,rdel ; (1-k)*sample[addr]
cho rda, rmp0,0,rdel+1 ; k*sample[addr+1] + ACC
wra dtemp, 0 ; Save it off to memory and clear ACC
cho rda, rmp0,rptr2|compc, rdel ; (1-k)*sample[addr+ half ramp]
cho rda, rmp0,rptr2,rdel+1 ; k*sample[addr+ half ramp + 1] + ACC
cho sof, rmp0,na|compc,0 ; Result in ACC, multiply it by (1-XFADE) coefficient
cho rda, rmp0,na,dtemp ; Add in earlier value saved in memory, multiply saved value by XFADE coefficient
wrax dacr, 0 ; Write it to DACL and clear ACC
skp ZRO,END ;unconditional skip to END
SWOFF: ;switch is off so pass signal through
ldax ADCL ;overwrite acc with left input
wrax DACL,0 ;write to left output then clear acc
rdax ADCR,1 ;load right input into acc
wrax DACR,0 ;write to right output then clear acc
END: