Octave up and down

Algorithm development and general DSP issues

Moderator: frank

Sweetalk
Posts: 141
Joined: Thu Oct 15, 2009 5:13 am

Post by Sweetalk »

frank wrote:Sorry, forgot all about this thread... give this a try:

Code: Select all

delayd mem 4096 ; Down delay
temp mem 1 ; Temp location for partial calculations
; 
skp run,START

;
wldr RMP0,16384,4096
wldr RMP1,-8192,4096
; 
START: ldax ADCL
; Write it to left delay and clear ACC
wra delayd,0
; Read in left
ldax ADCL
;
wra delayd,0
; 
cho rda,RMP0,REG|COMPC,delayd
cho rda,RMP0,,delayd+1
wra temp,0
cho rda,RMP0,RPTR2|COMPC,delayd
cho rda,RMP0,RPTR2,delayd+1
cho sof,RMP0,NA|COMPC,0
cho rda,RMP0,NA,temp
mulx POT1
wrax REG0,0
;
cho rda,RMP1,REG|COMPC,delayd
cho rda,RMP1,,delayd+1
wra temp,0
cho rda,RMP1,RPTR2|COMPC,delayd
cho rda,RMP1,RPTR2,delayd+1
cho sof,RMP1,NA|COMPC,0
cho rda,RMP1,NA,temp
MULX POT2
wrax REG1,0
;
ldax ADCL
mulx POT0
rdax REG0,1.0
rdax REG1,1.0
wrax DACL,1.0
wrax DACR,0
Hey Frank!, I was working on this code modifying it and trying to make an octave up block for another program and when I was reading it came with an instruction that is not on the instruction set of the Spin website: LDAX. For what I can understand you use only to read from the left ADC, is the same as RDAX?. I remember trying this code in the past and worked like a charm, but today I came across this and makes me doubt.

Also, the first portion of the code is for octave up (RMP0, controlled by POT1) and the second for octave down (RMP1, controlled by POT2)?. I haven't got any FV-1 here to try it.
frank
Posts: 1244
Joined: Wed Oct 19, 2005 12:26 pm
Contact:

Post by frank »

Sweetalk wrote: Hey Frank!, I was working on this code modifying it and trying to make an octave up block for another program and when I was reading it came with an instruction that is not on the instruction set of the Spin website: LDAX. For what I can understand you use only to read from the left ADC, is the same as RDAX?. I remember trying this code in the past and worked like a charm, but today I came across this and makes me doubt.

Also, the first portion of the code is for octave up (RMP0, controlled by POT1) and the second for octave down (RMP1, controlled by POT2)?. I haven't got any FV-1 here to try it.
LDAX is a pseudo opcode (see page 59 of the SpinAsm pdf), it codes to an RDFX with a 0 as coefficient so it basically clears the ACC and loads the value from the register directly into ACC.

The POTs are controlling the volume levels of the calculated signal after octave up or down. So you can mix in just a little or a lot of the pitched signals.
Frank Thomson
Experimental Noize
Sweetalk
Posts: 141
Joined: Thu Oct 15, 2009 5:13 am

Post by Sweetalk »

frank wrote:
Sweetalk wrote: Hey Frank!, I was working on this code modifying it and trying to make an octave up block for another program and when I was reading it came with an instruction that is not on the instruction set of the Spin website: LDAX. For what I can understand you use only to read from the left ADC, is the same as RDAX?. I remember trying this code in the past and worked like a charm, but today I came across this and makes me doubt.

Also, the first portion of the code is for octave up (RMP0, controlled by POT1) and the second for octave down (RMP1, controlled by POT2)?. I haven't got any FV-1 here to try it.
LDAX is a pseudo opcode (see page 59 of the SpinAsm pdf), it codes to an RDFX with a 0 as coefficient so it basically clears the ACC and loads the value from the register directly into ACC.

The POTs are controlling the volume levels of the calculated signal after octave up or down. So you can mix in just a little or a lot of the pitched signals.
Thank you!
Alex MAK
Posts: 89
Joined: Fri Nov 05, 2010 1:00 pm

Post by Alex MAK »

Hi, Frank! I built the code Octaver with chorus, and it helped to smooth out fluctuations. But I see too much of a chorus, and the surge is not entirely gone. What are tips and tricks? Thank you! Alex :)

Code: Select all

;OCTAVER+ Alex MAK

;Pot0 = Clean
;Pot1 = OCT+1
;pot2 = OCT-1
;memory declarations:
delayd	mem	4096	; Down delay
temp	mem	1	; Temp location for partial
mem	chodel	5000

;register equates:

equ	mono	reg0
equ	choout	reg5
equ	oct1	reg6
equ	oct2	reg7


;clear registers and initialize LFOs:

skp	run,endclr
wlds	sin0,12,100
wlds	sin1,0,800
wldr	RMP0,16384,4096
wldr	RMP1,-8192,4096
endclr:

;--------------------------------------------------
; Do octave up and down

; Read in left

rdax	adcl,1   
; Write it to left delay and clear ACC
wra	delayd,0

cho rda,RMP0,REG|COMPC,delayd
cho rda,RMP0,,delayd+1
wra temp,0
cho rda,RMP0,RPTR2|COMPC,delayd
cho rda,RMP0,RPTR2,delayd+1
cho sof,RMP0,NA|COMPC,0
cho rda,RMP0,NA,temp
mulx POT1
wrax oct1,0
;
cho rda,RMP1,REG|COMPC,delayd
cho rda,RMP1,,delayd+1
wra temp,0
cho rda,RMP1,RPTR2|COMPC,delayd
cho rda,RMP1,RPTR2,delayd+1
cho sof,RMP1,NA|COMPC,0
cho rda,RMP1,NA,temp
MULX POT2
wrax oct2,0

;--------------------------------------------------


;now do chorus, prepare pot1 for rate, driving SIN1:

sof	0.01,0.01	;approx. 1Hz to 3 Hz
wrax	sin1_rate,0	;load sin1 rate register

;do chorus from chorus delay:


cho	rda,sin1,sin|reg|compa,chodel+1600
cho	rda,sin1,sin|compc|compa,chodel+1601

cho	rda,sin1,cos|reg|compa,chodel+900
cho	rda,sin1,cos|compc|compa,chodel+901


;combine signals:



ldax    ADCL
mulx    POT0
rdax    oct1,1
rdax    oct2,1
wra	chodel,1
rdax	choout,0.5
;sof	1,0.02
wrax	dacl,0
;sof	-0.04,-0.04
wrax	dacr,0


Sweetalk
Posts: 141
Joined: Thu Oct 15, 2009 5:13 am

Post by Sweetalk »

Code: Select all

rdax    oct1,1
rdax    oct2,1
wra   chodel,1
rdax   choout,0.5
Here I found a "problem"... You mix the 2 octaves and then you write them down to the chorus memory and let the two octaves on the ACC, then mix with the chorus output. I rather clean the ACC and then read from the chorus output like this:

Code: Select all

rdax oct1, 1
rdax oct2, 1
wra chodel, 0
rdax choout, 0.5
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