Spin Semiconductor

I'm having some trouble with the CHO SOF instruction. The format of the instruction is inconsistent. The knowledge base section of the Spin Web site lists the format as:

cho sof,rmp1,na ;multiply ACC value by ramp1 crossfade value

If you enter that into the assembler it will complain with:

<0000>[ Pass 2] [ 1002] Line: 100 "cho sof,rmp1,reg " - ERROR:Operand or comma missing - Operand 4

If you feed it:

cho sof,rmp1,na,0

...it will now assemble, but the operation doesn't seem to follow that this is a scale ACC by the value of the LFO instruction. I just found Keith's cheat sheet and it says:

CHO SOF,lfo,param,addrs ACC=ACC*value+ for performing crossfade (pitch transposition)

That shows an address in the instruction at operand 4 and then "ACC=ACC*value+" ends with the question, plus what? Playing with the 4th operand, it is assembled as a floating point value rather than an address, and the values it creates don't seem to make sense. For example:

0115 80000014 :cho sof,sin0, 0,0
0116 80000014 :cho sof,sin0, 0,-1
0117 80019994 :cho sof,sin0, 0,.1
0118 800E6694 :cho sof,sin0, 0,-.1
0119 800FFFF4 :cho sof,sin0, 0,.99999
0120 80000034 :cho sof,sin0, 0,-.99999

Note that you can specify +.99999 which should be out of range, and that 0 and -1 both assemble to zeros.


I'm trying to get the regular and RPTR2 versions of a ramp into ACC.

cho rdal, rmp1 works great but the assembler won't allow specification of the RPTR2 option. How can I extract the LFO value using the CHO SOF variant? I tried replacing the above with:

sof 0,.999
cho sof,rmp1,reg,0

and

clr
or %01111111_11111111_11111111
cho sof,rmp1,reg,0

They don't seem to work as I would assume. Please help. Thank You.

PS: If the above info turns up to be a bug in the assembler and maintenance is required, is there any chance we (the users) could get a new instruction that would simply specify a 32 bit value for that location?, and is there any chance of supporting "cho rdal,rmp1,rptr2"? Pretty please?

OK, now I see that the 4th operand is assembled as a 15 bit address from a positive fraction. Negative values are treated as 1-value.

Sorry for the delay in posting, been out of the office.

Looks like you got it figured out, I'll look into the "cho rdal" with an rptr2 but I have a feeling it isn't supported in the chip. I'll have to look at the schematics but I think in the "cho rdal" the LFO is read prior to the LFO manipulation performed control bits like COMPC, NA, etc.

No worries on the tiny delay. It's fantastic to amazing that the designers are available so readily.

I figured out the format the assembler is using for operand 4 (which seems to be 'inert' in the coded instruction) but am still looking for analogs of CHO RDAL. I know CHO RDAL, COSx was added as a revision so at least the sin osc control bits are accessible which gives me hope but in the mean time is there a workaround?

I'm starting with this:

cho rdal, rmp1
wrax addr_ptr, 0

Looking at your example pitch shifting code, I found an example of a functioning CHO SOF. Using that example, the following substitution seems like it should at least work but does not:

sof 0,.999
cho sof,rmp1,reg,0
wrax addr_ptr, 0

To give the scale part of the CHO more to work with I also replaced the sof 0,.999 with...

clr
or %01111111_11111111_11111111

...thinking this is the largest possible positive value?

The code in question uses a pair of these LFO reads with one offset. I have removed a lot of clicking using the snippet below for the 2nd read but still don't understand exactly why.

cho rdal, rmp1
xor %01100000_00000000_00000000
wrax addr_ptr, 0

If you specify a ramp with an amplitude of 4095, how will those bits map to the addr_ptr register when using CHO RDAL?

Thank you for your help, Frank.

Just an FYI, I haven't forgotten about your questions, have not had the chance yet this week to sit at the design computer and bring up the schematics. Been one of those weeks so far...

No problem. I understand. It's been one of those weeks for me too. There are plenty of other pieces of code to work on in the mean time.

Next task is to rig together an I2C interface to burn EEPROMs and test out the potential "cho rdal,rptr2" instruction. If I find anything useful, I'll post it.

OK, so, lets see here (looks at chip schematic):

The 4th operand in CHO SOF is actually an address so you can address different areas of delay RAM

CHO RDAL with a ramp should map the ramp to bits [21:0] with bits [23:22] set to 0 in the accumulator. This is not effected by the amplitude set for the ramp as the wave is taken prior to scaling

Your XOR then is basically off-setting the ramp by portion of the period:
Ramp Post-XOR
0x000000 0x600000
0x200000 0x400000
0x3fffff 0x5fffff

It may be better with a: xor %00100000_00000000_00000000
since 0x3fffff is the max ramp value you will get a 1/2 period off-set:
Ramp Post-XOR
0x000000 0x200000
0x100000 0x300000
0x200000 0x000000
0x3fffff 0x1fffff

Finally, accumulator bits [22:8] are the bits sent to the addr_ptr register