Few questions

Algorithm development and general DSP issues

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gm1
Posts: 2
Joined: Wed Nov 18, 2009 9:35 pm

Few questions

Post by gm1 »

So here they are:

1. I'm feeding the FV 1 with audio on one channel and timing pulses on the other channel, I want a part of the code to be edge triggered by those pulses. I'm trying to create a conditional skp based on those incoming timing pulse, but it does not work for me. I want to synchronize an event on the FV1 to the BPM clock pulses coming from a computer.

Any suggestions or other ideas how to do that?


2 . What are the HEX value of the ADC at -1.0, 0 and 0.99


3. I'm experimenting with the bit crusher code posted on the forum and trying to replace the "and MASK" with a variable data reading from the pot "and pot0". It looks like all logic operation (and/xor/or) can work only with actual numbers and not with registers, is that correct. If so, any recommendation how to work out the bit crusher code to enable a pot control??


4. Any suggestion how to get the DAC to output voltage (no caps on the output ) that correspond to a pot movement.

I try this but it didn't work:

clr
rdax pot0 , 1
wrax adcl , 1

Thanks 8)
frank
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Joined: Wed Oct 19, 2005 12:26 pm
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Re: Few questions

Post by frank »

gm1 wrote:So here they are:

1. I'm feeding the FV 1 with audio on one channel and timing pulses on the other channel, I want a part of the code to be edge triggered by those pulses. I'm trying to create a conditional skp based on those incoming timing pulse, but it does not work for me. I want to synchronize an event on the FV1 to the BPM clock pulses coming from a computer.

Any suggestions or other ideas how to do that?
A SKP ZRC should be real usefule here, see this thread at the end for an example: http://www.spinsemi.com/forum/viewtopic.php?t=126
gm1 wrote:2 . What are the HEX value of the ADC at -1.0, 0 and 0.99
They should be 0x800000, 0x0, 0x7fffff All numbers in the FV-1 are 2's comp

gm1 wrote:3. I'm experimenting with the bit crusher code posted on the forum and trying to replace the "and MASK" with a variable data reading from the pot "and pot0". It looks like all logic operation (and/xor/or) can work only with actual numbers and not with registers, is that correct. If so, any recommendation how to work out the bit crusher code to enable a pot control??
Off the top of my head, I would try looking at the pot position then doing a skip to the desired AND to mask at that point. This should work if there are just a few mask values you want to use.
gm1 wrote:4. Any suggestion how to get the DAC to output voltage (no caps on the output ) that correspond to a pot movement.

I try this but it didn't work:

clr
rdax pot0 , 1
wrax adcl , 1
The DACs are delta-sigma converters and I believe they are filtered internally to remove any DC so I don't think this can work like this. You could use an LFO to generate a signal and use the pot to control the amplitude. Then externally filter it to get the amplitude and remove the LFO signal.
Frank Thomson
Experimental Noize
frank
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Joined: Wed Oct 19, 2005 12:26 pm
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Post by frank »

After some more research, the DACs will go down to DC. I tried it on my dev board and it worked fine. I ran the following:

Code: Select all

clr
rdax	pot0,1.0	; range 0 to .9999
sof	1.0,-0.5	; range -0.5 to 0.5
sof	-2.0,0	; range -1 to +1
wrax	dacl,0
Couple thing to keep in mind:
1. DAC output has a 1/2VCC offset, note that is accounted for in the above code.
2. Make sure dev board is on EXT and program 0
3. Make sure scope is DC coupled
Last edited by frank on Thu Nov 19, 2009 3:27 pm, edited 1 time in total.
Frank Thomson
Experimental Noize
frank
Posts: 1244
Joined: Wed Oct 19, 2005 12:26 pm
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Post by frank »

Oops, above code has a phase inversion, correct code here:

Code: Select all

clr
rdax	pot0,1.0	; range 0 to .9999
sof	1.0,-0.5	; range -0.5 to 0.5
sof	-2.0,0	; range -1 to +1
sof	-1.0,0	; phase correct
wrax	dacl,0
Frank Thomson
Experimental Noize
gm1
Posts: 2
Joined: Wed Nov 18, 2009 9:35 pm

Post by gm1 »

It works perfect :D

Thanks Frank!!
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