Shimmer

Algorithm development and general DSP issues

Moderator: frank

danielgiani
Posts: 7
Joined: Mon Dec 09, 2013 4:03 am

Post by danielgiani »

yes, I did it! But didnt succeed..
Hey Ho, Let's Go!
danielgiani
Posts: 7
Joined: Mon Dec 09, 2013 4:03 am

shimmer Level

Post by danielgiani »

danielgiani wrote:yes, I did it! But didnt succeed..
POT2 working! Thank you guys.

I do agree with Sweetalk when he suggested to add more shimmer (pitch shifter) volume in the reverb tail.
Im testing the effect and, in my opinion, is gets lost when blended with the guitar pure signal...

Any of you know how to make the pitch shifter section louder?
Hey Ho, Let's Go!
nilsonlav
Posts: 1
Joined: Sun Dec 15, 2013 8:16 am

code

Post by nilsonlav »

Sweetalk wrote:
Sweetalk wrote:Well, I been working a little bit on the shimmer algorithm with a different approach than the one posted earlier.

I tooked the Hall reverb, eliminated the predelay section. The signal flow intents to be like this:


INPUT ---> + ---> REVERB -------> OUTPUT
| |
|<--- PITCH <----|

The adder on the front it's controled by POT2, allowing to adjust the amount of pitch shifted signal going back to the reverb.

I haven't tried yet but I'll be nice if you can take a look at this and see if it's OK. I'll be trying it tomorrow I hope (not at the office right now)
Hello sweetalk, can you post the entire code with this new shimmer algorithm that you mentioned?

Regards
RickM
Posts: 2
Joined: Fri Jan 30, 2015 11:30 am
Contact:

Post by RickM »

Is this still being worked on? would love the updated code to play with
micahvdm
Posts: 7
Joined: Tue Sep 09, 2014 9:15 am

Post by micahvdm »

Sorry to bring up a really old thread, but does any one know how I would go about making the shimmer more pronounced in this code? any help will greatly appreciated!
tjm215
Posts: 18
Joined: Sun Dec 22, 2013 8:07 am

Post by tjm215 »

Code: Select all

SKP RUN ,1
WLDR 0, 16384, 4096
LDAX REG0
WRA 0,0.0
CHO RDA,2,REG | COMPC,0
CHO RDA,2,0,1
WRA 4097,0.0
CHO RDA,2,COMPC | RPTR2,0
CHO RDA,2,RPTR2,1
CHO SOF,2,COMPC | NA,0.0
CHO RDA,2,NA,4097
WRAX REG5,0.0000000000
RDAX ADCL,1.0000000000
WRAX REG6,0.0000000000
RDAX REG5,1.0000000000
MULX POT0
RDAX REG6,1.0000000000
WRAX REG6,0.0000000000
RDAX POT1,1.0000000000
SOF 0.5500000000,0.3000000000
WRAX REG10,0.0000000000
RDAX REG6,0.5000000000
RDA 11359,0.71
WRAP 11203,-0.71
RDA 11583,0.71
WRAP 11360,-0.71
RDA 11916,0.71
WRAP 11584,-0.71
RDA 12365,0.71
WRAP 11917,-0.71
WRAX REG11,0.0000000000
RDA 11202,1.0
MULX REG10
RDAX REG11,1.0000000000
RDA 17177,0.6
WRAP 15926,-0.6
RDA 18929,0.6
WRAP 17178,-0.6
WRAX REG9,1.0000000000
RDFX REG14,0.4000000000
WRLX REG14,-1.0000000000
RDFX REG13,0.0100000000
WRHX REG13,-1.0000000000
RDAX REG9,-1.0000000000
RDAX REG9,1.0000000000
WRA 12366,0.0
RDA 15925,1.0
MULX REG10
RDAX REG11,1.0000000000
RDA 23319,0.6
WRAP 21876,-0.6
RDA 24663,0.6
WRAP 23320,-0.6
WRAX REG9,1.0000000000
RDFX REG16,0.4000000000
WRLX REG16,-1.0000000000
RDFX REG15,0.0100000000
WRHX REG15,-1.0000000000
RDAX REG9,-1.0000000000
RDAX REG9,1.0000000000
WRA 18930,0.0
RDA 21875,1.0
MULX REG10
RDAX REG11,1.0000000000
RDA 30223,0.6
WRAP 28641,-0.6
RDA 32205,0.6
WRAP 30224,-0.6
WRAX REG9,1.0000000000
RDFX REG18,0.4000000000
WRLX REG18,-1.0000000000
RDFX REG17,0.0100000000
WRHX REG17,-1.0000000000
RDAX REG9,-1.0000000000
RDAX REG9,1.0000000000
WRA 24664,0.0
RDA 28640,1.0
MULX REG10
RDAX REG11,1.0000000000
RDA 5373,0.6
WRAP 4099,-0.6
RDA 6756,0.6
WRAP 5374,-0.6
WRAX REG9,1.0000000000
RDFX REG8,0.4000000000
WRLX REG8,-1.0000000000
RDFX REG7,0.0100000000
WRHX REG7,-1.0000000000
RDAX REG9,-1.0000000000
RDAX REG9,1.0000000000
WRA 6757,0.0
RDA 12366,0.8
RDA 20806,1.5
RDA 26757,1.1
RDA 9550,1.0
WRAX REG12,0.0000000000
RDA 12366,0.8
RDA 19853,1.5
RDA 25898,1.1
RDA 9024,1.0
WRAX REG19,0.0000000000
SKP RUN ,2
WLDS 0,35,50
WLDS 1,23,50
CHO RDA,0,REG | COMPC,15976
CHO RDA,0,0,15977
WRA 16026,0.0
CHO RDA,0,COS  | COMPC,21926
CHO RDA,0,COS ,21927
WRA 21976,0.0
CHO RDA,1,REG | COMPC,28691
CHO RDA,1,0,28692
WRA 28741,0.0
CHO RDA,1,COS  | COMPC,4149
CHO RDA,1,COS ,4150
WRA 4199,0.0
RDAX REG19,1.0000000000
WRAX REG0,0.0000000000
RDAX ADCL,-0.5000000000
RDAX REG12,0.5000000000
MULX POT2
RDAX ADCL,0.5000000000
WRAX REG20,0.0000000000
RDAX REG20,1.0000000000
WRAX DACL,0.0000000000
RDAX REG20,1.0000000000
WRAX DACR,0.0000000000
put this shimverb together with spin cad. sounds good on the simulator
ice-nine
Posts: 192
Joined: Thu May 24, 2012 9:03 am

Post by ice-nine »

Hi tjm,
I tried out the code above on a pedal and it is working quite nicely. Very nice amount of shimmer.

Just when this thread has been inactive for a long time 2 shimmers come along at once.

Here is one I was working on last night, it is a little more subtle than with controls for reverb decay, reverb level and shimmer reverb level.

Code: Select all

;New Shimmer Reverb Program
;from 3k Room
;09/01/2013 	rev 1.01 Mick Taylor
;22/11/2015 	rev 2.1 Set pre Delay: Reverb freq. response and gain changes Steve Mitchell/ Mick Taylor
;                   	pre delay removed for shimmer code space              
;07/12/2015  	Shimmer code added Mick Taylor

;Pot0 = Shimmer
;Pot1 = reverb level
;Pot2 = reverb time

mem	shimdel	4096	;delay for shimmer
mem	stemp	1
mem	idel	4000	;initial sound space  122mS
mem	iap0	11
mem	iap1	27
mem	iap2	43
mem	iap5	171
mem	iap6	296	;thickening all passes embedded in initial delay

mem	ap1	134         ;4.1mS
mem	ap2	256         ;7.8mS
mem	ap3	562         ;17.1mS
mem	ap4	763	;reverb loop input all passes 

mem	lap1a	1421       ;43mS
mem	lap1b	1945       ;59mS
mem	d1	2434       ;74mS
mem	lap2a	1894       ;58mS
mem	lap2b	1767       ;54mS
mem	d2	2645	 ;80.7mS  : loop constants 

;write constants registers

equ	kd	-0.5	;damping coefficient (for shelving)

;write-first registers:

equ	dry	reg0
equ	rev_in	reg1
equ	kirt	reg2	;coefficient to scale initial sound
equ	krt	reg3	;coefficient to affect RT of loop
equ	apout	reg4	;output of loop input all passes
equ	temp	reg5	;temp register for filter routines
equ	gain	reg6	;adjust gain with RT
equ	revout	reg7
equ   	pitchout  reg8   	;octave up output 

;read-first registers:

equ	lf1	reg20	;reverb loop filter 1
equ	lf2	reg21	;reverb loop filter 2
equ	hf1	reg22	;loop high pass 1 (fixed)
equ	hf2	reg23	;loop high pass 2 (fixed)
equ	lfin1	reg24	;LPF for imbedding in intial delay
equ	lfin2	reg25	;LPF for imbedding in intial delay
equ	lf	reg26	;input low pass (shelving with kd)
equ	lpfp	reg27

equ   	lpfk   	0.3      	;lpf coefficent for lpfp after pitch shifting 1.85kHz 
equ   	lpfs   	-0.5      	;Shelving coefficent for lpfp

;clear read-first registers:

skp	run,endclr
wrax	lf1,0
wrax	lf2,0
wrax	hf1,0
wrax	hf2,0
wrax	lfin1,0
wrax	lfin2,0
wrax	lf,0
endclr:

;initial sound tap positions (30.5uS/location, 100=3.05mS):

equ	ld1	874		;first tap, left   26.7mS
equ	rd1	874		;first tap, right 26.7mS
equ	ld2	1156		;and so on...    35.3mS
equ	rd2	962                   	;29.3mS
equ	ld3	1345                 	;41mS
equ	rd3	1121               	;34.2mS
equ	ld4	1456               	;44.4mS
equ	rd4	1423            	;43.4mS
equ	ld5	2121            	;64.7mS
equ	rd5	2124           	;64.7mS
equ	ld6	3245             	;99mS
equ	rd6	3646             	;111.2mS

;initialize sin LFO:

skp	run,endset
wlds	sin0,25,100
wldr 	RMP0,16384,4096   	;load octave up 
endset:
;--------------Off and Running Program Loops to Here--------------------------
;prepare decay pot: Reverb Time

rdax	pot2,0.97	;get pot, limit to less than infinite
wrax	krt,1		;write loop decay time
sof	0.4,0.6		;scale Pot to 0.6 to 1.0 range
wrax	kirt,1		;write impulse filter gains changed to 1 from 0 (MT 22-11-15) gain always +0.99 before=too high
sof	-0.88,0.99         	;scale to decrease gain with RT:need to assess the -1 & the 0.99 range offset for  gain Vs RT now changed to -0.88
			; Range allowed=-2.0 to +0.9999389: e.g. From scale above if pot2=0.6 then 0.6*(-0.88)+0.99=0.46;if pot2=1 then gain=0.11 (23-11-2015)
wrax	gain,0		;write gain factor and clear ACC

;------------------------------Octave up------------------------------------ 

cho 	rda,RMP0,REG|COMPC,shimdel 
cho 	rda,RMP0,,shimdel+1 
wra    	stemp,0 
cho 	rda,RMP0,RPTR2|COMPC,shimdel 
cho 	rda,RMP0,RPTR2,shimdel+1 
cho 	sof,RMP0,NA|COMPC,0 
cho 	rda,RMP0,NA,stemp 
mulx    	POT0 
rdfx   	lpfp,   lpfk      			;Freq coef 
wrhx   	lpfp,   lpfs      			;Shelving coef. 
wrax    	pitchout,0 

;-------------do inputs to predelay:------------------- 
;rdax	pitchout,1
rdax	adcl,0.5
rdax	adcr,0.5			;get inputs sum & divide by 2
wrax	dry,1			;22/11/2015 write dry input signal to dry register and keep in ACC for mulx next instruction:
mulx	gain			;Acc=Acc*[reg] give greater gain to short RT See code above for adjusting this 23-11-2015(Steve)
wrax	rev_in,1			;22/11/2015 write gain adjusted dry input to rev_in register and clear ACC: Reg1
wra	shimdel,0
;--------------------read predelay and write initial all pass response delay:------------------

rdax	pitchout,1
rdax	rev_in, 0.5             	;use 97mS delayed signal divided by 2 for reverb input
rda	iap0#,0.5              	;Read from end of initial all pass memory0 divide by 2 adding to rev_in data
wrap	iap0,-0.5		;complicate input to initial delay
wrax	temp,1                  	; Write ACC to register;multiply ACC x 1.         
rdfx	lf,0.404              		;Low pass <2.7kHz
wrhx	lf,-1                      	;Register=ACC; ACC=ACC*(-1)+previous contents of ACC
mulx	kd                         	;ACC=ACC*[Reg];  kd = damping coefficient for shelving from POT0
rdax	temp,1			;low pass filter entire input
wra	idel,0			;write initial sound delay  clear ACC

;complicate initial sound:

rda	idel+500,1            	;read from 15.2mS position Retain ACC
rda	iap1#,0.5               	;read from end of iap1 delay stream divided by 2 
wrap	iap1,-0.5               	;write to beginning of iap1,
wra	idel+500,0            	;[data at delay ram address]=ACC; ACC=ACC*0 , i.e. clear ACC

rda	idel+1000,1           	;read from 30.5mS position
rda	iap2#,0.5               	;read from end of iap2 delay stream divided by 2 
wrap	iap2,-0.5               	;write to beginning of iap2,
wrax	temp,1			;save filter input
rdfx	lfin1,0.2                	;0.2=~1.2kHz perhaps too high for Abbey Road reverb try 600Hz = 0.109
wrhx	lfin1,-1			;make HP filter
mulx	kd			;multiply by negative shelving coef
rdax	temp,1			;add back input (shelving LPF)
wra	idel+1000,0          	;now modify idel+1000 but clear ACC

rda	idel+2500,1          	;read from 76.3mS position retain ACC
rda	iap5#,0.5
wrap	iap5,-0.5
wrax	temp,1			;save filter input
rdfx	lfin2,0.2                	;0.2 =~1.2kHz
wrhx	lfin2,-1			;make HP filter
mulx	kd			;multiply by negative shelving coef
rdax	temp,1			;add back input (shelving LPF)
wra	idel+2500,0          	;[data at delay ram address]=ACC; ACC=ACC*0 , i.e. clear ACC


rda	idel+3000,1          	;read from 91.5mS position retain ACC
rda	iap6#,0.5
wrap	iap6,-0.5
wra	idel+3000,0

;do reverb input all passes:

rda	idel,0.9			;leave some headroom:
rda	ap1#,0.5
wrap	ap1,-0.5
rda	ap2#,0.5
wrap	ap2,-0.5
rda	ap3#,0.5
wrap	ap3,-0.5
rda	ap4#,0.5
wrap	ap4,-0.5
wrax	apout,0                  	;Save all pass out to 

;do reverb loop and sum all outputs:

rda	d2#,1                   	;Read from end of d2, retain ACC
mulx	krt                        	;krt = Reverb Time coefficient
rdax	apout,1	
rda	lap1a#,0.5
wrap	lap1a,-0.5
rda	lap1b#,0.5
wrap	lap1b,-0.5
wrax	temp,1			;save filter input
rdfx	lf1,0.404               	;2.7kHz
wrhx	lf1,-1			;make LP filter 
mulx	kd			;multiply by negative shelving coef
rdax	temp,1			;add back temporary filter input keep ACC
rdfx	hf1,0.01                	;ACC=ACC+([reg]-ACC)*0.01
wrhx	hf1,-0.5			;roll out lows in loop
wra	d1,0                      	;Write sum to d1 location clear ACC

rda	d1#,1                  	;Read from end of d1 memory 
mulx	krt
rdax	apout,1
rda	lap2a#,0.5
wrap	lap2a,-0.5
rda	lap2b#,0.5
wrap	lap2b,-0.5
wrax	temp,1			
rdfx	lf2,0.404              	;Again use 2.7kHz
wrhx	lf2,-1			
mulx	kd			
rdax	temp,1	
rdfx	hf2,0.01
wrhx	hf2,-0.5				
wra	d2,1.99                
rda	d1,1.99                	
mulx	pot1                     	
mulx	pot1
wrax	revout,0              		;Reverb output saved to register, ACC cleared

;do reverb smoothing:

cho	rda,sin0,sin|reg|compc,d1+100
cho	rda,sin0,sin,d1+101
wra	d1+200,0

cho	rda,sin0,cos|reg|compc,d2+100
cho	rda,sin0,cos,d2+101
wra	d2+200,0

;now combine to output

rdax	dry,1                      	;
rdax	revout,1
wrax	dacl,0
ice-nine
Posts: 192
Joined: Thu May 24, 2012 9:03 am

Re: Shimmer

Post by ice-nine »

I'm reposting this Shimmer as when the forum was updated/ported over some codes were corrupted with page breaks or something that would not allow the copy and pasted code to compile without error. There were a lot of these &#58 added to the code for whatever reason.
So I have edited out the errors and re-posted this ShimmerVerb for anyone to try out.

Code: Select all

;New Shimmer Reverb Program
;from 3k Room
;09/01/2013 	rev 1.01 Mick Taylor
;22/11/2015 	rev 2.1 Set pre Delay Reverb freq. response and gain changes Steve Mitchell/ Mick Taylor
;                   	pre delay removed for shimmer code space              
;07/12/2015  	Shimmer code added Mick Taylor

;Pot0 = Shimmer
;Pot1 = reverb level
;Pot2 = reverb time

mem	shimdel	4096	;delay for shimmer
mem	stemp	1
mem	idel	4000	;initial sound space  122mS
mem	iap0	11
mem	iap1	27
mem	iap2	43
mem	iap5	171
mem	iap6	296	;thickening all passes embedded in initial delay

mem	ap1	134         ;4.1mS
mem	ap2	256         ;7.8mS
mem	ap3	562         ;17.1mS
mem	ap4	763	;reverb loop input all passes 

mem	lap1a	1421       ;43mS
mem	lap1b	1945       ;59mS
mem	d1	2434       ;74mS
mem	lap2a	1894       ;58mS
mem	lap2b	1767       ;54mS
mem	d2	2645	 ;80.7mS   loop constants 

;write constants registers

equ	kd	-0.5	;damping coefficient for shelving

;write-first registers

equ	dry	reg0
equ	rev_in	reg1
equ	kirt	reg2	;coefficient to scale initial sound
equ	krt	reg3	;coefficient to affect RT of loop
equ	apout	reg4	;output of loop input all passes
equ	temp	reg5	;temp register for filter routines
equ	gain	reg6	;adjust gain with RT
equ	revout	reg7
equ   	pitchout  reg8   	;octave up output 

;read-first registers;

equ	lf1	reg20	;reverb loop filter 1
equ	lf2	reg21	;reverb loop filter 2
equ	hf1	reg22	;loop high pass 1 fixed
equ	hf2	reg23	;loop high pass 2 fixed
equ	lfin1	reg24	;LPF for imbedding in initial delay
equ	lfin2	reg25	;LPF for imbedding in initial delay
equ	lf	reg26	;input low pass shelving with kd
equ	lpfp	reg27

equ   	lpfk   	0.3      	;lpf coefficent for lpfp after pitch shifting 1.85kHz 
equ   	lpfs   	-0.5      	;Shelving coefficent for lpfp

;clear read-first registers

skp	run,endclr
wrax	lf1,0
wrax	lf2,0
wrax	hf1,0
wrax	hf2,0
wrax	lfin1,0
wrax	lfin2,0
wrax	lf,0
endclr:

;initial sound tap positions 30.5uS/location, 100=3.05mS

equ	ld1	874		;first tap, left   26.7mS
equ	rd1	874		;first tap, right 26.7mS
equ	ld2	1156		;and so on...    35.3mS
equ	rd2	962                   	;29.3mS
equ	ld3	1345                 	;41mS
equ	rd3	1121               	;34.2mS
equ	ld4	1456               	;44.4mS
equ	rd4	1423            	;43.4mS
equ	ld5	2121            	;64.7mS
equ	rd5	2124           	;64.7mS
equ	ld6	3245             	;99mS
equ	rd6	3646             	;111.2mS

;initialize sin LFO

skp	run,endset
wlds	sin0,25,100
wldr 	RMP0,16384,4096   	;load octave up 
endset:
;--------------Off and Running Program Loops to Here--------------------------
;prepare decay pot Reverb Time

rdax	pot2,0.97	;get pot, limit to less than infinite
wrax	krt,1		;write loop decay time
sof	0.4,0.6		;scale Pot to 0.6 to 1.0 range
wrax	kirt,1		;write impulse filter gains changed to 1 from 0 MT 22-11-15 gain always +0.99 before=too high
sof	-0.88,0.99         	;scale to decrease gain with RT need to assess the -1 & the 0.99 range offset for  gain Vs RT now changed to -0.88
			; Range allowed=-2.0 to +0.9999389 e.g. From scale above if pot2=0.6 then 0.6* -0.88+0.99=0.46;if pot2=1 then gain=0.11 23-11-2015
wrax	gain,0		;write gain factor and clear ACC

;------------------------------Octave up------------------------------------ 

cho 	rda,RMP0,REG|COMPC,shimdel 
cho 	rda,RMP0,,shimdel+1 
wra    	stemp,0 
cho 	rda,RMP0,RPTR2|COMPC,shimdel 
cho 	rda,RMP0,RPTR2,shimdel+1 
cho 	sof,RMP0,NA|COMPC,0 
cho 	rda,RMP0,NA,stemp 
mulx    	POT0 
rdfx   	lpfp,   lpfk      			;Freq coef 
wrhx   	lpfp,   lpfs      			;Shelving coef. 
wrax    	pitchout,0 

;-------------do inputs to predelay------------------- 
;rdax	pitchout,1
rdax	adcl,0.5
rdax	adcr,0.5			;get inputs sum & divide by 2
wrax	dry,1			;22/11/2015 write dry input signal to dry register and keep in ACC for mulx next instruction:
mulx	gain			;Acc=Acc* reg& give greater gain to short RT See code above for adjusting this 23-11-2015 Steve
wrax	rev_in,1			;22/11/2015 write gain adjusted dry input to rev_in register and clear ACC Reg1
wra	shimdel,0
;--------------------read predelay and write initial all pass response delay------------------

rdax	pitchout,1
rdax	rev_in, 0.5             	;use 97mS delayed signal divided by 2 for reverb input
rda	iap0#,0.5              	;Read from end of initial all pass memory0 divide by 2 adding to rev_in data
wrap	iap0,-0.5		;complicate input to initial delay
wrax	temp,1                  	; Write ACC to register;multiply ACC x 1.         
rdfx	lf,0.404              		;Low pass <2.7kHz
wrhx	lf,-1                      	;Register=ACC; ACC=ACC*(-1)+previous contents of ACC
mulx	kd                         	;ACC=ACC*Reg  kd = damping coefficient for shelving from POT0
rdax	temp,1			;low pass filter entire input
wra	idel,0			;write initial sound delay  clear ACC

;complicate initial sound

rda	idel+500,1            	;read from 15.2mS position Retain ACC
rda	iap1#,0.5               	;read from end of iap1 delay stream divided by 2 
wrap	iap1,-0.5               	;write to beginning of iap1,
wra	idel+500,0            	;data at delay ram address=ACC; ACC=ACC*0 , i.e. clear ACC

rda	idel+1000,1           	;read from 30.5mS position
rda	iap2#,0.5               	;read from end of iap2 delay stream divided by 2 
wrap	iap2,-0.5               	;write to beginning of iap2,
wrax	temp,1			;save filter input
rdfx	lfin1,0.2                	;0.2=~1.2kHz perhaps too high for Abbey Road reverb try 600Hz = 0.109
wrhx	lfin1,-1			;make HP filter
mulx	kd			;multiply by negative shelving coef
rdax	temp,1			;add back input shelving LPF
wra	idel+1000,0          	;now modify idel+1000 but clear ACC

rda	idel+2500,1          	;read from 76.3mS position retain ACC
rda	iap5#,0.5
wrap	iap5,-0.5
wrax	temp,1			;save filter input
rdfx	lfin2,0.2                	;0.2 =~1.2kHz
wrhx	lfin2,-1			;make HP filter
mulx	kd			;multiply by negative shelving coef
rdax	temp,1			;add back input shelving LPF
wra	idel+2500,0          	;data at delay ram address=ACC; ACC=ACC*0 , i.e. clear ACC


rda	idel+3000,1          	;read from 91.5mS position retain ACC
rda	iap6#,0.5
wrap	iap6,-0.5
wra	idel+3000,0

;do reverb input all passes

rda	idel,0.9			;leave some headroom
rda	ap1#,0.5
wrap	ap1,-0.5
rda	ap2#,0.5
wrap	ap2,-0.5
rda	ap3#,0.5
wrap	ap3,-0.5
rda	ap4#,0.5
wrap	ap4,-0.5
wrax	apout,0                  	;Save all pass out to 

;do reverb loop and sum all outputs

rda	d2#,1                   	;Read from end of d2, retain ACC
mulx	krt                        	;krt = Reverb Time coefficient
rdax	apout,1	
rda	lap1a#,0.5
wrap	lap1a,-0.5
rda	lap1b#,0.5
wrap	lap1b,-0.5
wrax	temp,1			;save filter input
rdfx	lf1,0.404               	;2.7kHz
wrhx	lf1,-1			;make LP filter 
mulx	kd			;multiply by negative shelving coef
rdax	temp,1			;add back temporary filter input keep ACC
rdfx	hf1,0.01                	;ACC=ACC+reg-ACC*0.01
wrhx	hf1,-0.5			;roll out lows in loop
wra	d1,0                      	;Write sum to d1 location clear ACC

rda	d1#,1                  	;Read from end of d1 memory 
mulx	krt
rdax	apout,1
rda	lap2a#,0.5
wrap	lap2a,-0.5
rda	lap2b#,0.5
wrap	lap2b,-0.5
wrax	temp,1			
rdfx	lf2,0.404              	;Again use 2.7kHz
wrhx	lf2,-1			
mulx	kd			
rdax	temp,1	
rdfx	hf2,0.01
wrhx	hf2,-0.5				
wra	d2,1.99                
rda	d1,1.99                	
mulx	pot1                     	
mulx	pot1
wrax	revout,0              		;Reverb output saved to register, ACC cleared

;do reverb smoothing

cho	rda,sin0,sin|reg|compc,d1+100
cho	rda,sin0,sin,d1+101
wra	d1+200,0

cho	rda,sin0,cos|reg|compc,d2+100
cho	rda,sin0,cos,d2+101
wra	d2+200,0

;now combine to output

rdax	dry,1                      	;
rdax	revout,1
wrax	dacl,0
www.stanleyfx.co.uk
"It's fairly straight forward, if you want to start it press start, you can work out the rest of the controls yourself."
Zerikin
Posts: 2
Joined: Mon Apr 16, 2018 10:00 am

Re: Shimmer

Post by Zerikin »

I've been using this reverb program some. Trying to get a nice shimmer for ambient swells but it's shimmering a bit too fast I think. Is there a way to adjust the rate of the shimmer?
Aaron
Posts: 54
Joined: Wed Mar 04, 2015 8:10 pm
Location: Oklahoma

Re: Shimmer

Post by Aaron »

You can try adding some delay to pitchout before reading it back into the input...
DrAlx
Posts: 25
Joined: Wed Feb 20, 2019 11:01 am
Location: Surrey, UK

Re: Shimmer

Post by DrAlx »

Aaron wrote: Wed Mar 20, 2019 9:38 am You can try adding some delay to pitchout before reading it back into the input...
Exactly what I did when writing shimmer code for my DIY Tonewoodamp.
The following code is pretty much that with some unnecessary stuff (for my acoustic guitar) removed.
It's all wet. Uncomment line near bottom to add dry.

Code: Select all

; Reverb + Shimmer (Version 6) by DrAlx (Alex Lawrow)
;
; This routine is based on Mick Taylor's (Ice-9s) reverb loop
; and shimmer code with some changes such as:
;
;  1) Prime numbers for delay line lengths.
;  2) More linear mapping of pot sweep to reverb time.
;  3) Anti-aliasing filter before the pitch-shifter.
;  4) Shimmer level is controlled by feeding both the input signal
;      and the reverb output into the pitch-shifter in varying amounts.
;  5) Pitch-shifted signal is fed into a delay line to give a couple of short delays.
;     This lets the shimmer effect build up slowly in time.
;  6) Output is 100% wet.  Uncomment line at bottom to add dry signal.

;POT0 = Reverb time (0 to 10 seconds).
;POT1 = Amount of treble in reverb loop.
;POT2 = Shimmer level

MEM	tmp	1	; Temp memory for octave-up
MEM	octave	4096	; Delay line for octave-up
MEM	echos	14831	; Delay line for echos after octave up

; 4 AP filters, just before the reverb loop
MEM	ap1	137
MEM	ap2	257
MEM	ap3	563
MEM	ap4	761
; The reverb loop AP filters
MEM	lap1a	1423
MEM	lap1b	1949
MEM	lap2a	1759
MEM	lap2b	1889
; The reverb loop delay lines
MEM	d1	2437
MEM	d2	2647

; Registers
EQU	temp		REG0	; Temp register for filter routines and other stuff
EQU	dry		REG1	; Dry signal
EQU	krt		REG2	; Reverb decay coefficient
EQU	apout		REG3	; Output of input APs.  For injection into reverb loop
EQU	rev_out		REG4	; Reverb output
EQU	kd		REG5	; Coefficient for shelving LPF filters in reverb loop
EQU	lp_antialias	REG6	; Anti-alias LPF before octave up
EQU	lp1		REG7	; Loop LPF 1
EQU	lp2		REG8	; Loop LPF 2
EQU	hp1		REG9	; Loop HPF 1
EQU	hp2		REG10	; Loop HPF 2
EQU	octave_dry	REG11	; Amount of dry fed into octave-up
EQU	octave_rev	REG12	; Amount of reverb fed into octave-up

;-------------- Initialize LFOs etc -------------------
SKP	RUN,end_init
WLDS	SIN0,25,100		; Sin LFO for reverb "smoothing". (25 ==> ~1Hz)
WLDR	RMP0,16384,4096	; Ramp LFO for octave up.  (16384 ==> octave up)
end_init:
;-------------------------------------------------

;--------- Map control pots to gain factors ------------
; Map POT0 to reverb time (0 to 10 seconds)
;
; The shortest delay tap in the reverb loop is at 74.27ms.
; So the loop decay factor (krt) relates to RT60 reverb time (T) as follows (I think):
;      krt = 0.001 ^ ( 0.07427 / T ),				Eq(1)
;
; As POT0 goes from 0 to 1, try to make T increase linearly from 0s to 10s.
;      krt = 0.001 ^ ( 0.07427 / ( 0.001 + 10 * POT0 ) ), 	Eq(2)
;
; POT0   RT60(s)   krt    
; 0         0.001     0.00
; 1.0      10.00     0.95
;
; Eq(2) would be a nightmare to implement, so use this approximation 
;    krt = 0.95 * POT0 ^ ( 0.185 * ( 1 - POT0 ) )		Eq(3)

RDAX	POT0,1		; Read POT0 (full sweep is 0 to 1)
SOF	-0.185,0.185
WRAX 	temp,0
RDAX	POT0,1
LOG	1,0
MULX	temp
EXP	0.95,0  
WRAX 	krt,0		; krt = 0.95 * POT0 ^ ( 0.185 * ( 1 - POT0 ) )

; Map POT1 to control the shelving LPFs in the reverb loop
RDAX	POT1,1			; Read POT1
SOF	0.5,-0.5
WRAX	kd,0			; kd = -0.5 to 0 (i.e. clockwise to increase treble)

; Map POT2 to shimmer gain in two stages.
; First half turn increases reverb output into octaveup (from a factor of 0 to 0.2).
; Next half turn increases dry signal into the octaveup (from a factor of 0 to 1)
SOF	0,0.2
WRAX	octave_rev,0		; Set default octave_rev to maximum (0.2)
RDAX 	POT2,1			; Read POT2 (full sweep is 0 to 1)	
SOF	1,-0.5			; ACC = -0.5 to 0.5
SKP	gez,set_octave_dry	; If >=0, set octave_dry, else overwrite default octave_rev and zero octave_dry
SOF	-2,0			; ACC = (1-x)  where x increases 0 to 1
WRAX 	temp,1			
MULX 	temp			; ACC = (1-x)^2 			
MULX 	temp			; ACC = (1-x)^3 
MULX 	temp			; ACC = (1-x)^4
SOF	-0.2,0.2			; ACC = 0.2 -  0.2 * (1-x)^4
WRAX	octave_rev,0		; Write to octave_rev, then clear ACC to zero octave_dry
set_octave_dry:
sof	1.999,0
WRAX	octave_dry,0		; Set octave_dry (0 to 1)
;-------------------------------------------------


;---------- Take average of L and R inputs -----------
RDAX	ADCL,0.5
RDAX	ADCR,0.5
WRAX	dry,1			; Write to dry
;-------------------------------------------------


;----------- Make input signal for octave up ----------
MULX	octave_dry		; ACC already contains dry
WRAX	temp,0			; temp = dry * octave_dry		 
RDAX	rev_out,1	
MULX	octave_rev
RDAX	temp,1			; ACC = dry * octave_dry  + rev_out * octave_rev
;-------------------------------------------------


;--------- Anti-alias LPF before the octave up ---------
RDFX	lp_antialias, 0.544		; 4096 Hz ==> 1 - exp(-2*pi*4096/32768) ==> 0.544
WRAX	lp_antialias, 1
WRA	octave,0			; Write to octave up
;-------------------------------------------------


;------------- Octave up fed into delay --------------
CHO	RDA,RMP0,REG|COMPC,octave
CHO	RDA,RMP0,,octave+1
WRA	tmp,0
CHO	RDA,RMP0,RPTR2|COMPC,octave
CHO	RDA,RMP0,RPTR2,octave+1
CHO	SOF,RMP0,NA|COMPC,0
CHO	RDA,RMP0,NA,tmp

WRA	echos,0		; Write to start of echos delay line
;-------------------------------------------------


;------------- Make reverb input signal --------------
RDA	echos^,1		; Read echo from middle of delay line
RDA	echos#,1		; Add echo from end of delay line
RDAX	dry,1		; Add in dry signal
;-------------------------------------------------


;----------- 4 APs before the reverb loop ------------
RDA	ap1#,0.5
WRAP	ap1,-0.5
RDA	ap2#,0.5
WRAP	ap2,-0.5
RDA	ap3#,0.5
WRAP	ap3,-0.5
RDA	ap4#,0.5
WRAP	ap4,-0.5
WRAX	apout,0		; apout will get injected (twice) into the reverb loop

;---------------- Begin reverb loop -----------------
RDA	d2#,1		; Read from end of d2
MULX	krt		; Scale by krt
RDAX	apout,0.5	; Inject 0.5 * apout
RDA	lap1a#,0.5	; 1st loop AP filter before d1
WRAP	lap1a,-0.5	; ...
RDA	lap1b#,0.5	; 2nd loop AP filter before d1 
WRAP	lap1b,-0.5	; ...

;Adjustable shelved LPF (DC Gain = 1, Corner = 2700 Hz)
WRAX	temp,1		; Save input
RDFX	lp1,0.404	; 0.404 = 1 - exp(-2*pi*2700/32768)
WRHX	lp1,-1		; 
MULX	kd		; Multiply by damping coefficient
RDAX	temp,1		; Add back input

;Shelved HPF (DC Gain = 0.5, Corner = 53 Hz)      
RDFX	hp1,0.01		; 0.01 = 1 - exp(-2*pi*53/32768)
WRHX	hp1,-0.5		; -0.5 = DC Gain - 1
WRA	d1,0		; Write to start of d1

RDA	d1#,1		; Read from end of d1
MULX	krt		; Scale by krt	
RDAX	apout,0.5	; Inject 0.5 * apout
RDA	lap2a#,0.5	; 1st loop AP filter before d2
WRAP	lap2a,-0.5	; ...
RDA	lap2b#,0.5	; 2nd loop AP filter before d2
WRAP	lap2b,-0.5	; ...

;Adjustable shelved LPF (DC Gain = 1, Corner = 2700 Hz)
WRAX	temp,1		; Save input
RDFX	lp2,0.404	; 0.404 = 1 - exp(-2*pi*2700/32768)
WRHX	lp2,-1		; 
MULX	kd		; Multiply by damping coefficient	
RDAX	temp,1		; Add back input

;Shelved HPF (DC Gain = 0.5, Corner = 53 Hz)    	
RDFX	hp2,0.01		; 0.01 = 1 - exp(-2*pi*53/32768)
WRHX	hp2,-0.5		; -0.5 = DC Gain - 1
WRA	d2,0		; Write to start of d2
;---------------- End reverb loop ------------------


;-- Reverb smoothing (modulate delay lines in the loop) --
CHO	RDA,SIN0,REG|SIN|COMPC,d1+100
CHO	RDA,SIN0,SIN,d1+101
WRA	d1+200,0

CHO	RDA,SIN0,REG|COS|COMPC,d2+100
CHO	RDA,SIN0,COS,d2+101
WRA	d2+200,0
;-------------------------------------------------


;------------ Make reverb output signal --------------
; Take output taps from start of loop delays
RDA	d1,1
RDA	d2,1
WRAX	rev_out,1		; Save reverb output to register
;-------------------------------------------------

;RDAX	dry,1		; Add dry signal
WRAX	DACL,0
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