Harmonizer
Moderator: frank
Harmonizer
Hello all guys! I want to do that Fv-1 worked Harmonizer . Are there the prepared decisions? Thank you!
There are 2 pitch shift blocks in the FV-1 so examine the pitch shift examples at http://www.spinsemi.com/Products/appnot ... N-0001.pdf and you should be able to program a harmonizer based on the info there.
Frank Thomson
Experimental Noize
Experimental Noize
That pdf includes example pitch shift code which is all a harmonizer is, shift the signal and add it back to the original. Just change the numbers to give the shift you want (a fifth, fourth, etc.) and that should do it.
Frank Thomson
Experimental Noize
Experimental Noize
Used parts of code of oсtaver and pitch shifter. Did not begin to work conducts a clean sound, on potentiometers irresponsive.
mem ldel 4096 ;left delay
mem dtemp 1 ;temporary DRAM data location
; Initialization, only run on first executuion of code
; Skip the following two instructions if NOT the first time
skp RUN, LOOP
wldr 0, 0, 4096 ; Load up a ramp LFO to shift up 0 octaves, A=0x0 (4096 range)
LOOP:
START: ldax ADCL
; Write it to left delay and clear ACC
wra delayd,0
; Read in left
ldax ADCL
;
cho rda, rmp0,reg|compc,ldel ; (1-k)*sample[addr]
cho rda, rmp0,0,ldel+1 ; k*sample[addr+1] + ACC
wra dtemp, 0 ; Save it off to memory and clear ACC
cho rda, rmp0,rptr2|compc, ldel ; (1-k)*sample[addr+ half ramp]
cho rda, rmp0,rptr2,ldel+1 ; k*sample[addr+ half ramp + 1] + ACC
cho sof, rmp0,na|compc,0 ; Result in ACC, multiply it by (1-XFADE) coefficient
cho rda, rmp0,na,dtemp
mulx POT1
wrax REG0,0
;
cho rda, rmp0,reg|compc,ldel ; (1-k)*sample[addr]
cho rda, rmp0,0,ldel+1 ; k*sample[addr+1] + ACC
wra dtemp, 0 ; Save it off to memory and clear ACC
cho rda, rmp0,rptr2|compc, ldel ; (1-k)*sample[addr+ half ramp]
cho rda, rmp0,rptr2,ldel+1 ; k*sample[addr+ half ramp + 1] + ACC
cho sof, rmp0,na|compc,0 ; Result in ACC, multiply it by (1-XFADE) coefficient
cho rda, rmp0,na,dtemp
MULX POT2
wrax REG1,0
;
ldax ADCL
mulx POT0
rdax REG0,1.0
rdax REG1,1.0
wrax DACL,1.0
wrax DACR,0
mem ldel 4096 ;left delay
mem dtemp 1 ;temporary DRAM data location
; Initialization, only run on first executuion of code
; Skip the following two instructions if NOT the first time
skp RUN, LOOP
wldr 0, 0, 4096 ; Load up a ramp LFO to shift up 0 octaves, A=0x0 (4096 range)
LOOP:
START: ldax ADCL
; Write it to left delay and clear ACC
wra delayd,0
; Read in left
ldax ADCL
;
cho rda, rmp0,reg|compc,ldel ; (1-k)*sample[addr]
cho rda, rmp0,0,ldel+1 ; k*sample[addr+1] + ACC
wra dtemp, 0 ; Save it off to memory and clear ACC
cho rda, rmp0,rptr2|compc, ldel ; (1-k)*sample[addr+ half ramp]
cho rda, rmp0,rptr2,ldel+1 ; k*sample[addr+ half ramp + 1] + ACC
cho sof, rmp0,na|compc,0 ; Result in ACC, multiply it by (1-XFADE) coefficient
cho rda, rmp0,na,dtemp
mulx POT1
wrax REG0,0
;
cho rda, rmp0,reg|compc,ldel ; (1-k)*sample[addr]
cho rda, rmp0,0,ldel+1 ; k*sample[addr+1] + ACC
wra dtemp, 0 ; Save it off to memory and clear ACC
cho rda, rmp0,rptr2|compc, ldel ; (1-k)*sample[addr+ half ramp]
cho rda, rmp0,rptr2,ldel+1 ; k*sample[addr+ half ramp + 1] + ACC
cho sof, rmp0,na|compc,0 ; Result in ACC, multiply it by (1-XFADE) coefficient
cho rda, rmp0,na,dtemp
MULX POT2
wrax REG1,0
;
ldax ADCL
mulx POT0
rdax REG0,1.0
rdax REG1,1.0
wrax DACL,1.0
wrax DACR,0
Try doing one thing at a time (i.e. just the pitch shift) and when that works add in one small item and when that works add in one small item...
Only way to debug n a chip like this, start with working code and make small changes and test they work.
Only way to debug n a chip like this, start with working code and make small changes and test they work.
Frank Thomson
Experimental Noize
Experimental Noize
Frank, I did as you advised, whew for me turned out:
;PITCH TRANSPOSER, STEREO
mem ldel 4096 ;left delay
mem dtemp 1 ;temporary DRAM data location
equ potfil reg0 ;pot0 filter for smoothing
; Initialization, only run on first executuion of code
; Skip the following two instructions if NOT the first time
skp RUN, LOOP
wldr 0, 0, 4096 ; Load up a ramp LFO to shift up 0 octaves, A=0x0 (4096 range)
LOOP:
rdax ADCL, 1.0 ;read left input
wra ldel, 0.0 ;write to delay start
; We use the base of the sample memory block as the
; address since we are using a positive only ramp
; that ranges 0 to 1.0 (4095 in this case)
;do left chan:
cho rda, rmp0,reg|compc,ldel ; (1-k)*sample[addr]
cho rda, rmp0,0,ldel+1 ; k*sample[addr+1] + ACC
wra dtemp, 0 ; Save it off to memory and clear ACC
cho rda, rmp0,rptr2|compc, ldel ; (1-k)*sample[addr+ half ramp]
cho rda, rmp0,rptr2,ldel+1 ; k*sample[addr+ half ramp + 1] + ACC
cho sof, rmp0,na|compc,0 ; Result in ACC, multiply it by (1-XFADE) coefficient
cho rda, rmp0,na,dtemp ; Add in earlier value saved in memory, multiply saved value by XFADE coefficient
wrax dacl, 0 ; Write it to DACL and clear ACC
rdax pot0,1.0
sof 0.25,-0.125 ;control ranges +/-0.125
rdfx potfil,0.02 ;filter result to smooth pot control
wrax potfil,1.0
wrax rmp0_rate,0 ;write to rate of lfo2, clear accumulator
cho rda, rmp1,reg|compc,ldel ; (1-k)*sample[addr]
cho rda, rmp1,0,ldel+1 ; k*sample[addr+1] + ACC
wra dtemp, 0 ; Save it off to memory and clear ACC
cho rda, rmp1,rptr2|compc, ldel ; (1-k)*sample[addr+ half ramp]
cho rda, rmp1,rptr2,ldel+1 ; k*sample[addr+ half ramp + 1] + ACC
cho sof, rmp1,na|compc,0 ; Result in ACC, multiply it by (1-XFADE) coefficient
cho rda, rmp1,na,dtemp ; Add in earlier value saved in memory, multiply saved value by XFADE coefficient
wrax dacl, 0 ; Write it to DACL and clear ACC
rdax pot1,1.0
sof 0.25,-0.125 ;control ranges +/-0.125
rdfx potfil,0.02 ;filter result to smooth pot control
wrax potfil,1.0
wrax rmp1_rate,0 ;write to rate of lfo2, clear accumulator
Problem that a device works as one, but not as 2 separate
;PITCH TRANSPOSER, STEREO
mem ldel 4096 ;left delay
mem dtemp 1 ;temporary DRAM data location
equ potfil reg0 ;pot0 filter for smoothing
; Initialization, only run on first executuion of code
; Skip the following two instructions if NOT the first time
skp RUN, LOOP
wldr 0, 0, 4096 ; Load up a ramp LFO to shift up 0 octaves, A=0x0 (4096 range)
LOOP:
rdax ADCL, 1.0 ;read left input
wra ldel, 0.0 ;write to delay start
; We use the base of the sample memory block as the
; address since we are using a positive only ramp
; that ranges 0 to 1.0 (4095 in this case)
;do left chan:
cho rda, rmp0,reg|compc,ldel ; (1-k)*sample[addr]
cho rda, rmp0,0,ldel+1 ; k*sample[addr+1] + ACC
wra dtemp, 0 ; Save it off to memory and clear ACC
cho rda, rmp0,rptr2|compc, ldel ; (1-k)*sample[addr+ half ramp]
cho rda, rmp0,rptr2,ldel+1 ; k*sample[addr+ half ramp + 1] + ACC
cho sof, rmp0,na|compc,0 ; Result in ACC, multiply it by (1-XFADE) coefficient
cho rda, rmp0,na,dtemp ; Add in earlier value saved in memory, multiply saved value by XFADE coefficient
wrax dacl, 0 ; Write it to DACL and clear ACC
rdax pot0,1.0
sof 0.25,-0.125 ;control ranges +/-0.125
rdfx potfil,0.02 ;filter result to smooth pot control
wrax potfil,1.0
wrax rmp0_rate,0 ;write to rate of lfo2, clear accumulator
cho rda, rmp1,reg|compc,ldel ; (1-k)*sample[addr]
cho rda, rmp1,0,ldel+1 ; k*sample[addr+1] + ACC
wra dtemp, 0 ; Save it off to memory and clear ACC
cho rda, rmp1,rptr2|compc, ldel ; (1-k)*sample[addr+ half ramp]
cho rda, rmp1,rptr2,ldel+1 ; k*sample[addr+ half ramp + 1] + ACC
cho sof, rmp1,na|compc,0 ; Result in ACC, multiply it by (1-XFADE) coefficient
cho rda, rmp1,na,dtemp ; Add in earlier value saved in memory, multiply saved value by XFADE coefficient
wrax dacl, 0 ; Write it to DACL and clear ACC
rdax pot1,1.0
sof 0.25,-0.125 ;control ranges +/-0.125
rdfx potfil,0.02 ;filter result to smooth pot control
wrax potfil,1.0
wrax rmp1_rate,0 ;write to rate of lfo2, clear accumulator
Problem that a device works as one, but not as 2 separate
I have not run the code but 2 items jump out at me:
1. You need a second wldr in the start routine to initialize ramp 1
2. You do a 'wrax dacl,0' after each ramp, this means the output of ramp 1 is overwriting the value ramp 0 just wrote there. Write the result of ramp 0 to a temp register then after ramp1 add in the temp reg so acc has both results added together then write it to dacl
1. You need a second wldr in the start routine to initialize ramp 1
2. You do a 'wrax dacl,0' after each ramp, this means the output of ramp 1 is overwriting the value ramp 0 just wrote there. Write the result of ramp 0 to a temp register then after ramp1 add in the temp reg so acc has both results added together then write it to dacl
Frank Thomson
Experimental Noize
Experimental Noize
Try th following code, it also adds the original signal back in:
Code: Select all
;PITCH TRANSPOSER, STEREO
mem ldel 4096 ;left delay
mem dtemp 1
equ potfil reg0 ;pot0 filter for smoothing
equ potfil2 reg1
equ temp1 reg2
;equ dtemp reg2
; Initialization, only run on first executuion of code
; Skip the following two instructions if NOT the first time
skp RUN, LOOP
wldr 0, 0, 4096 ; Load up a ramp LFO to shift up 0 octaves, A=0x0 (4096 range)
wldr 1, 0, 4096 ; Load up a ramp LFO to shift up 0 octaves, A=0x0 (4096 range)
LOOP:
rdax ADCL, 1.0 ;read left input
wra ldel, 0.0 ;write to delay start
; We use the base of the sample memory block as the
; address since we are using a positive only ramp
; that ranges 0 to 1.0 (4095 in this case)
;do left chan:
cho rda, rmp0,reg|compc,ldel ; (1-k)*sample[addr]
cho rda, rmp0,0,ldel+1 ; k*sample[addr+1] + ACC
wra dtemp, 0 ; Save it off to memory and clear ACC
cho rda, rmp0,rptr2|compc, ldel ; (1-k)*sample[addr+ half ramp]
cho rda, rmp0,rptr2,ldel+1 ; k*sample[addr+ half ramp + 1] + ACC
cho sof, rmp0,na|compc,0 ; Result in ACC, multiply it by (1-XFADE) coefficient
cho rda, rmp0,na,dtemp ; Add in earlier value saved in memory, multiply saved value by XFADE coefficient
wrax temp1, 0 ; Write it to DACL and clear ACC
rdax pot0,1.0
sof 0.25,-0.125 ;control ranges +/-0.125
rdfx potfil,0.02 ;filter result to smooth pot control
wrax potfil,1.0
wrax rmp0_rate,0 ;write to rate of lfo2, clear accumulator
cho rda, rmp1,reg|compc,ldel ; (1-k)*sample[addr]
cho rda, rmp1,0,ldel+1 ; k*sample[addr+1] + ACC
wra dtemp, 0 ; Save it off to memory and clear ACC
cho rda, rmp1,rptr2|compc, ldel ; (1-k)*sample[addr+ half ramp]
cho rda, rmp1,rptr2,ldel+1 ; k*sample[addr+ half ramp + 1] + ACC
cho sof, rmp1,na|compc,0 ; Result in ACC, multiply it by (1-XFADE) coefficient
cho rda, rmp1,na,dtemp ; Add in earlier value saved in memory, multiply saved value by XFADE coefficient
rdax temp1,1.0 ; add in above shift
rdax adcl, 1.0 ; add in original signal
wrax dacl, 0 ; Write it to DACL and clear ACC
rdax pot1,1.0
sof 0.25,-0.125 ;control ranges +/-0.125
rdfx potfil2,0.02 ;filter result to smooth pot control
wrax potfil2,1.0
wrax rmp1_rate,0 ;write to rate of lfo2, clear accumulator
Frank Thomson
Experimental Noize
Experimental Noize