FV-1 I2C interface timing
Posted: Fri Feb 25, 2011 8:21 am
Hi Frank,
I am trying to load programs to FV1 directly from an ARM microcontroller. As for the 32768 Hz quartz the SCL clock of FV-1 runs at approximately 260 kHz, there is a critical timing on the I2C interface. The question is:
Must the SDA data be stable before the rising edge of the SCL?
If yes, what is the minimum setup time of SDA state before rising edge of the SCL?
If no, what is the minimum setup time of SDA state before falling edge of the SCL?
Thank you in advance.
I am trying to load programs to FV1 directly from an ARM microcontroller. As for the 32768 Hz quartz the SCL clock of FV-1 runs at approximately 260 kHz, there is a critical timing on the I2C interface. The question is:
Must the SDA data be stable before the rising edge of the SCL?
If yes, what is the minimum setup time of SDA state before rising edge of the SCL?
If no, what is the minimum setup time of SDA state before falling edge of the SCL?
Thank you in advance.