Spin Semiconductor

Hi Frank,

I am trying to load programs to FV1 directly from an ARM microcontroller. As for the 32768 Hz quartz the SCL clock of FV-1 runs at approximately 260 kHz, there is a critical timing on the I2C interface. The question is:

Must the SDA data be stable before the rising edge of the SCL?

If yes, what is the minimum setup time of SDA state before rising edge of the SCL?

If no, what is the minimum setup time of SDA state before falling edge of the SCL?

Thank you in advance.

SDA is only allowed to change while SCL is low (see section 4 of 24LC32A data sheet). I don't remember if I strobe the SDA line at rising clock or middle of high period but to be safe you should change SDA after falling edge of SCL.

As for set up, if I'm using rising edge of SCL to strobe the data then it should only need a few nanoseconds of setup time. If I'm strobing in the middle then no problem, as long as data is stable during SCL high it should be fine. I'll try to bring up the schematics later today and see where the data is strobed.

When reading I'm doing a sequential read (see section 8 of 24LC32A data sheet).

Datasheet for 24ls32a at http://ww1.microchip.com/downloads/en/D ... 21713L.pdf

"I don't remember if I strobe the SDA line at rising clock or middle of high period".

Please check this and let me know.

Appears data is registered about middle of high portion of clock so make sure data is stable from rising edge to falling edge of clock.