First of all I thank you for your work.
My English is not very good, I hope so apologies in advance.
I want your help with something.
I'm working on a patch ROM PITCH TRANSPOSER .
I'm trying to get exactly half notes. I want to scale the POT0 value through software.
I measured each half note the corresponding resistance values. (POT0)
I've found the following values:
(+5 semitone) - (full tone) - (-4 semitone).
By considering these values, I made arrangements on the software. But somehow I could not run the way my request.
I want to do the following:
POT0 -> middle position -> full note (no transposition)
POT0 -> in the right half position - Step by step -4 semitone
POT0 -> in the left half position - Step by step +5 semitone
I would ask you to help examine the following code.
Code: Select all
**********
; PITCH TRANSPOSER
; Revised
mem ldel 4096 ;left delay
mem dtemp 1 ;temporary DRAM data location
equ potfil reg0 ;pot0 filter for smoothing
;******02.07.2015 Kenan ******* Samples
equ LBL_VAL0 0.5 ; Pitch +5 semitone E G
equ LBL_VAL1 0.4 ; Pitch +4 semitone F G#
equ LBL_VAL2 0.3 ; Pitch +3 semitone F# A
equ LBL_VAL3 0.2 ; Pitch +2 semitone G Bb
equ LBL_VAL4 0.1 ; Pitch +1 semitone G# B
equ LBL_VAL5 0 ; Pitch 0 A C
equ LBL_VAL6 -0.1 ; Pitch -1 semitone Bb C#
equ LBL_VAL7 -0.2 ; Pitch -2 semitone B D
equ LBL_VAL8 -0.35 ; Pitch -3 semitone C Eb
equ LBL_VAL9 -0.5 ; Pitch -4 semitone C# E
;*************
; Initialization, only run on first executuion of code
; Skip the following two instructions if NOT the first time
skp RUN, LOOP
wldr 0,0,4096 ; Load up a ramp LFO to shift up 0 octaves, A=0x0 (4096 range)
LOOP:
ldax ADCL ;read left input
wra ldel, 0.0 ;write to delay start
; We use the base of the sample memory block as the
; address since we are using a positive only ramp
; that ranges 0 to 1.0 (4095 in this case)
; do left chan:
cho rda, rmp0,reg|compc,ldel ; (1-k)*sample[addr]
cho rda, rmp0,0,ldel+1 ; k*sample[addr+1] + ACC
wra dtemp, 0 ; Save it off to memory and clear ACC
cho rda, rmp0,rptr2|compc, ldel ; (1-k)*sample[addr+ half ramp]
cho rda, rmp0,rptr2,ldel+1 ; k*sample[addr+ half ramp + 1] + ACC
cho sof, rmp0,na|compc,0 ; Result in ACC, multiply it by (1-XFADE) coefficient
cho rda, rmp0,na,dtemp ; Add in earlier value saved in memory, multiply saved value by XFADE coefficient
wrax dacl, 0 ; Write it to DACL and clear ACC
;******02.07.2015 *******
ldax pot0
and %01111000_00000000_00000000
skp zro,LBL0 ; Pitch +5 semitone
sof 1,-0.1
skp zro,LBL1 ; Pitch +4 semitone
sof 1,-0.1
skp zro,LBL2 ; Pitch +3 semitone
sof 1,-0.1
skp zro,LBL3 ; Pitch +2 semitone
sof 1,-0.1
skp zro,LBL4 ; Pitch +1 semitone
sof 1,-0.1
skp zro,LBL5 ; Pitch 0
sof 1,-0.1
skp zro,LBL6 ; Pitch -1 semitone
sof 1,-0.1
skp zro,LBL7 ; Pitch -2 semitone
sof 1,-0.1
skp zro,LBL8 ; Pitch -3 semitone
sof 1,-0.1
skp zro,LBL9 ; Pitch -4 semitone
LBL0:
sof 0,LBL_VAL0
wrax potfil,0
skp zro,LBL_OUT
LBL1:
sof 0,LBL_VAL1
wrax potfil,0
skp zro,LBL_OUT
LBL2:
sof 0,LBL_VAL2
wrax potfil,0
skp zro,LBL_OUT
LBL3:
sof 0,LBL_VAL3
wrax potfil,0
skp zro,LBL_OUT
LBL4:
sof 0,LBL_VAL4
wrax potfil,0
skp zro,LBL_OUT
LBL5:
sof 0,LBL_VAL5
wrax potfil,0
skp zro,LBL_OUT
LBL6:
sof 0,LBL_VAL6
wrax potfil,0
skp zro,LBL_OUT
LBL7:
sof 0,LBL_VAL7
wrax potfil,0
skp zro,LBL_OUT
LBL8:
sof 0,LBL_VAL8
wrax potfil,0
skp zro,LBL_OUT
LBL9:
sof 0,LBL_VAL9
wrax potfil,0
skp zro,LBL_OUT
; **************
LBL_OUT:
ldax POT0 ; Read POT0 into ACC
mulx potfil ; Move from no pitch shift (0) to value set by "pitch" value
wrax RMP0_RATE,0 ; Load ACC into ramp rate register and clear ACC
**********