Spin Semiconductor

I would try to clock the FV1 with a simple op amp VCO instead of the knowledge base circuits, as I would like to modulate its frequency via CV.

I have a couple of questions:

-How precise should be the 50% duty cycle of a square wave generator used to clock the FV1?

-Which must be the peak to peak level of the square wave?

thanks in advance for your help!

sandromatik wrote: -How precise should be the 50% duty cycle of a square wave generator used to clock the FV1?

We never tested that parameter but it should be as close to 50% as possible. I expect the PLL to be a bit forgiving.

sandromatik wrote: -Which must be the peak to peak level of the square wave?

Normal 3.3V logic levels so I would target 0.8V to 2.5V minimum and 0 to 3.3V max.

OK Frank!

Can you predict which issues will cause a poor clock symmetry within the audio performance of the chip?

thanks again

The primary problem would be the PLL unable to lock to the clock signal, this would cause multiple audible issues in the chip. I expect the PLL will be forgiving to a clock that is not 50%, just not sure how much, but I suggest you make up the circuit and just test it. We did design the FV-1 to work across a wide range of issues and the PLL was designed to lock to a wide range of signals but we never actually worked out min/max duty cycle.

Any luck with this, sandromatik? I'm interested in variable clock, but I think there might be issues with the range of frequency, speed of modulation, as well as (maybe) symmetry. Would love to have the benefit of your experience. Thanks!

I'm interested to hear how this sounds, perhaps the LTC1799 would be a good candidate for teh clock signal. what audible effect would this have?

I place ltc1799s into the alesis hr16 drum machine replacing the clock line to the asic, by modulating the clock signal I get an 'overall' pitch control for the machine.

TipTop Audio advertise external sample clock as a feature of their FV-1 based ZDSP3000. Their documentation implies that it works over quite a wide range (not exactly defined) modulo aliasing issues.