CHO interpolation
Posted: Tue Nov 18, 2014 4:49 pm
I can't seem to wrap my head around this interpolation thing that two consecutive CHO RDA instructions do...
From the rom_pitch.spn:
cho rda, rmp0,reg|compc,ldel ; (1-k)*sample[addr]
cho rda, rmp0,0,ldel+1 ; k*sample[addr+1] + ACC
My understanding is that these back to back CHO instructions interpolate to a value between two actual samples... but which two? Are we interpolating between 2 ldel samples or 2 rmp0 samples? Are the k fractional bits from ldel or rmp0?
I have to assume that every instruction in a .spn file is exectued on every clock cycle... therefore, ldel in the first CHO is the same value as ldel+1 in the second CHO, because 1 clock cycle has elapsed and another sample was added to the beginning of ldel. Is this correct???
From the rom_pitch.spn:
cho rda, rmp0,reg|compc,ldel ; (1-k)*sample[addr]
cho rda, rmp0,0,ldel+1 ; k*sample[addr+1] + ACC
My understanding is that these back to back CHO instructions interpolate to a value between two actual samples... but which two? Are we interpolating between 2 ldel samples or 2 rmp0 samples? Are the k fractional bits from ldel or rmp0?
I have to assume that every instruction in a .spn file is exectued on every clock cycle... therefore, ldel in the first CHO is the same value as ldel+1 in the second CHO, because 1 clock cycle has elapsed and another sample was added to the beginning of ldel. Is this correct???