Clock Frequency Range When Driving X1 From a uP
Posted: Fri Sep 11, 2015 3:14 pm
I've been using the FV-1 for reverb for several years now.
Recently the need has come up for a circuit to generate two sine waves in quadrature that have a linear frequency relationship to a clock signal sent from a micro-controller's timer. Example: 6400Hz clock would yield 400Hz sine waves in quadrature at the output of the DACs.
It occurred to me that the FV-1 might be able to do this. I altered the code of the sample signal generator program to output the sine and cosine signals to the left and right channels. I am feeding the X1 input with the output of the uP timer, and using a voltage divider network to ensure the timer clock into X1 is less than 3.3V.
It seems to work well, except at low clock frequencies (below 4kHz clock), at which the output becomes unstable, and the sine waveforms look like they're broken up into six to eight big stair steps. My theory is that the internal PLL has an unpublished lower frequency limit where it can no longer synthesize the required DSP clock signal. Am I correct?
I can work around this by doubling or quadrupling the timer frequency, but I'd like to know the limitations.
The application is basically a low-noise signal generator for a motor controller. I'll publish more details on the application once I get it working better.
Robert
Recently the need has come up for a circuit to generate two sine waves in quadrature that have a linear frequency relationship to a clock signal sent from a micro-controller's timer. Example: 6400Hz clock would yield 400Hz sine waves in quadrature at the output of the DACs.
It occurred to me that the FV-1 might be able to do this. I altered the code of the sample signal generator program to output the sine and cosine signals to the left and right channels. I am feeding the X1 input with the output of the uP timer, and using a voltage divider network to ensure the timer clock into X1 is less than 3.3V.
It seems to work well, except at low clock frequencies (below 4kHz clock), at which the output becomes unstable, and the sine waveforms look like they're broken up into six to eight big stair steps. My theory is that the internal PLL has an unpublished lower frequency limit where it can no longer synthesize the required DSP clock signal. Am I correct?
I can work around this by doubling or quadrupling the timer frequency, but I'd like to know the limitations.
The application is basically a low-noise signal generator for a motor controller. I'll publish more details on the application once I get it working better.
Robert