Time and Pitch Shifting

Software questions and issues with the FV-1

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adventure_audio
Posts: 12
Joined: Mon Feb 02, 2015 9:19 pm

Time and Pitch Shifting

Post by adventure_audio »

Hey There,

I put together a little program to delay the signal 0-1000ms and would like to implement some pitch shifting to do +/-20 cents from the original signal.

Can someone point me in the right direction?

Thanks!

Code: Select all

RDAX ADCL,1.0000000000
WRA 0,0.0
CLR
OR $007FFF00
MULX POT0
RDFX REG1,0.0012500000
WRAX REG1,1.0000000000
SOF 0.9759826660,0.0000305176
WRAX ADDR_PTR,0.0000000000
RMPA 1.0
WRAX REG0,0.0000000000
;------ Output
RDAX REG0,1.0000000000
WRAX DACL,0.0000000000
Aaron
Posts: 54
Joined: Wed Mar 04, 2015 8:10 pm
Location: Oklahoma

Post by Aaron »

I ran into this issue a few months back. Unfortuantely you will need 513 spaces of memory for the pitch shifting so your delay will be limited to around 984ms unless you use a slower crystal. Are you wanting to delay the pitch shift, pitch shift the delay, or run the pitch shift in parallel with the delay?
adventure_audio
Posts: 12
Joined: Mon Feb 02, 2015 9:19 pm

Post by adventure_audio »

The idea is to have one input and two outputs. I would like to use the right out on the FV-1 to use as a "thru" and only alter the left output.

I wouldn't mind compromising the delay time in order to open up some memory and commands for the pitch shift.

Which would be more command intensive?

Pitch shifting -> delay
or
Delay -> pitch shift
ice-nine
Posts: 192
Joined: Thu May 24, 2012 9:03 am

Post by ice-nine »

Can you clarify what you want as I am a bit confused.

I read it as the following

Right out put = clean
left output = delayed signal plus -/+ 20cents pitch controlled by a pot.

Is this what you are wanting?
adventure_audio
Posts: 12
Joined: Mon Feb 02, 2015 9:19 pm

Post by adventure_audio »

Yes thats exactly what I am trying to do.
Sweetalk
Posts: 141
Joined: Thu Oct 15, 2009 5:13 am

Post by Sweetalk »

adventure_audio wrote:Yes thats exactly what I am trying to do.
Do the dry signal analog, it's a nonsense to get it pass thru the adc/dac and not process it.
Aaron
Posts: 54
Joined: Wed Mar 04, 2015 8:10 pm
Location: Oklahoma

Post by Aaron »

In experimenting with this I have found that you can indeed have the full delay space reserved for the delay and use this same memory block for the pitch shift. So all you will need to do is setup the delay the same and use that memory block in the pitch shift algo. When calculating the pitch shift just remember that there are 1200 cents in one octave.
adventure_audio
Posts: 12
Joined: Mon Feb 02, 2015 9:19 pm

Post by adventure_audio »

I wish that I could use a separate analog output for my 'thru' jack but this project will have another program that will use both outputs. So for consistency, I need to code a thru output on the right channel.

Thanks for the link! Looks like I have a bit of reading to do about ramps and pitch shifting.

This pitch shifting code from user tiriviri_2002

http://www.spinsemi.com/forum/viewtopic ... itch+shift

I have audibly tested use two sample buffers being crossfaded from each other. The problem is that the crossfade is audible. How would I manipulate the crossfade ADSR for a smoother transition?

It appears that this is a common problem for pitch shifting with the FV-1.

Code: Select all

; PITCH TRANSPOSER 
; Revised 

mem   ldel   4096   ;left delay 
mem   dtemp   1   ;temporary DRAM data location 

equ   potfil   reg0   ;pot0 filter for smoothing 

;******02.07.2015 Kenan *******             Samples 
equ   LBL_VAL0   0.5   ; Pitch +5 semitone   E   G 
equ   LBL_VAL1   0.4   ; Pitch +4 semitone   F   G# 
equ   LBL_VAL2   0.3   ; Pitch +3 semitone   F#   A 
equ   LBL_VAL3   0.2   ; Pitch +2 semitone   G   Bb 
equ   LBL_VAL4   0.1    ; Pitch +1 semitone   G#   B 
equ   LBL_VAL5   0       ; Pitch 0      A   C 
equ   LBL_VAL6   -0.1   ; Pitch -1 semitone   Bb   C# 
equ   LBL_VAL7   -0.2   ; Pitch -2 semitone   B   D 
equ   LBL_VAL8   -0.35   ; Pitch -3 semitone   C   Eb 
equ   LBL_VAL9   -0.5   ; Pitch -4 semitone   C#   E 
;************* 

; Initialization, only run on first executuion of code 
; Skip the following two instructions if NOT the first time 

skp   RUN, LOOP 
wldr    0,0,4096   ; Load up a ramp LFO to shift up 0 octaves, A=0x0 (4096 range) 
LOOP: 

ldax    ADCL      ;read left input 
wra    ldel, 0.0   ;write to delay start 

; We use the base of the sample memory block as the 
; address since we are using a positive only ramp 
; that ranges 0 to 1.0 (4095 in this case) 

; do left chan: 
cho    rda,   rmp0,reg|compc,ldel   ; (1-k)*sample[addr] 
cho    rda,   rmp0,0,ldel+1      ; k*sample[addr+1] + ACC 
wra    dtemp,   0         ; Save it off to memory and clear ACC 
cho    rda,   rmp0,rptr2|compc, ldel   ; (1-k)*sample[addr+ half ramp] 
cho    rda,   rmp0,rptr2,ldel+1   ; k*sample[addr+ half ramp + 1] + ACC 
cho    sof,    rmp0,na|compc,0      ; Result in ACC, multiply it by (1-XFADE) coefficient 
cho    rda,   rmp0,na,dtemp      ; Add in earlier value saved in memory, multiply saved value by XFADE coefficient 
wrax    dacl,   0          ; Write it to DACL and clear ACC 



;******02.07.2015 ******* 
ldax pot0 
and %01111000_00000000_00000000 
skp zro,LBL0    ; Pitch +5 semitone 
sof 1,-0.1      

skp zro,LBL1    ; Pitch +4 semitone 
sof 1,-0.1      

skp zro,LBL2    ; Pitch +3 semitone 
sof 1,-0.1      

skp zro,LBL3    ; Pitch +2 semitone 
sof 1,-0.1      

skp zro,LBL4      ; Pitch +1 semitone 
sof 1,-0.1      

skp zro,LBL5    ; Pitch 0 
sof 1,-0.1      

skp zro,LBL6    ; Pitch -1 semitone 
sof 1,-0.1      

skp zro,LBL7    ; Pitch -2 semitone 
sof 1,-0.1      

skp zro,LBL8    ; Pitch -3 semitone 
sof 1,-0.1  

skp zro,LBL9    ; Pitch -4 semitone 

LBL0:      
sof 0,LBL_VAL0 
wrax potfil,0 
skp zro,LBL_OUT 

LBL1:      
sof 0,LBL_VAL1 
wrax potfil,0 
skp zro,LBL_OUT 

LBL2: 
sof 0,LBL_VAL2 
wrax potfil,0 
skp zro,LBL_OUT 

LBL3: 
sof 0,LBL_VAL3 
wrax potfil,0 
skp zro,LBL_OUT 

LBL4: 
sof 0,LBL_VAL4 
wrax potfil,0 
skp zro,LBL_OUT 

LBL5: 
sof 0,LBL_VAL5 
wrax potfil,0 
skp zro,LBL_OUT 

LBL6: 
sof 0,LBL_VAL6 
wrax potfil,0 
skp zro,LBL_OUT 

LBL7: 
sof 0,LBL_VAL7 
wrax potfil,0 
skp zro,LBL_OUT 

LBL8: 
sof 0,LBL_VAL8 
wrax potfil,0 
skp zro,LBL_OUT 

LBL9: 
sof 0,LBL_VAL9 
wrax potfil,0 
skp zro,LBL_OUT 

; ************** 

LBL_OUT: 
ldax POT0       ; Read POT0 into ACC 
mulx potfil       ; Move from no pitch shift (0) to value set by "pitch" value 
wrax RMP0_RATE,0    ; Load ACC into ramp rate register and clear ACC 

I found this other crossfading thread that may help.

http://www.spinsemi.com/forum/viewtopic.php?t=533[/code]
frank
Posts: 1244
Joined: Wed Oct 19, 2005 12:26 pm
Contact:

Post by frank »

You really can't minimize the effect, real time pitch shifting will always have audible artifacts.
Frank Thomson
Experimental Noize
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