OEM1_1 Large Hall reverb true stereo conversion

Algorithm development and general DSP issues

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gkaiomenos
Posts: 19
Joined: Thu Oct 16, 2014 11:59 am

OEM1_1 Large Hall reverb true stereo conversion

Post by gkaiomenos »

Hi guys
I've been fond of this reverb lately but it's supposed to work as a mono in stereo out.
Is there any way in making it true stereo???
Any help appreciated
Digital Larry
Posts: 338
Joined: Mon Nov 12, 2012 1:12 pm
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Post by Digital Larry »

Can you copy the code here?
gkaiomenos
Posts: 19
Joined: Thu Oct 16, 2014 11:59 am

Post by gkaiomenos »

Yap here it is:

;OEM1_1 Large Hall reverb

;pot0 = reverb decay time
;pot1 = predelay (0-100mS at Fs=46KHz)
;pot2 = damping, increases with clockwise rotation

;The large hall has a rough initial sound with eventual high impulse density.

;The frequency response is somewhat colorful, which may threaten feedback
;in PA applications.

;the algorithm incorporates variable predelay to give better clarity to the
;initial sound.

;Vibrato is added within the reverb delay elements to smooth the decay and
;simulate natural convection currents.

;Input is expected to be mono, from single effects send, output is placed stereo.

mem pdel 4600
mem iap1 156
mem iap2 223
mem iap3 332
mem iap4 448
;
mem ap1 1251
mem ap1b 1751
mem ap2 1443
mem ap2b 1343
mem ap3 1582
mem ap3b 1981
mem ap4 1274
mem ap4b 1382
;
mem del1 3559
mem del2 2945
mem del3 3976
mem del4 4445

equ temp reg0
equ hpf1 reg1
equ hpf2 reg2
equ hpf3 reg3
equ hpf4 reg4
equ lpf1 reg5
equ lpf2 reg6
equ lpf3 reg7
equ lpf4 reg8
equ rt reg9
equ iapout reg10
equ pdelo reg11

;constants:

equ kfh 0.01
equ kfl 0.4
equ kiap 0.5
equ klap 0.6

;prepare decay time pot:

rdax pot0,1
sof 0.65,0.3
wrax rt,0 ;rt ranges 0.3 to 0.95

;do variable predelay:

skp run,1
wldr rmp0,0,4096 ;initialize predelay

rdax adcl,0.5 ;put inputs into predelay
rdax adcr,0.5
wra pdel,0

cho rda,rmp0,reg|compc,pdel ;get outputs from predelay, interpolated
cho rda,rmp0,0,pdel+1
wrax pdelo,0 ;write predelay output to register

cho rdal,rmp0 ;read current predelay pointer
rdax pot1,-0.5 ;subtract pot for servo control of pointer
wrax rmp0_rate,0 ;maintain predelay pointer

;now run predelayed signal into 4 all passes:

rdax pdelo,0.25 ;attenuate signal to avoid clipping
rda iap1#,kiap
wrap iap1,-kiap
rda iap2#,kiap
wrap iap2,-kiap
rda iap3#,kiap
wrap iap3,-kiap
rda iap4#,kiap
wrap iap4,-kiap
wrax iapout,0 ;write to register for ring injection

;now do reverb ring, use temp as reg for filtering:

;aps into delay1:

rda del4#,1 ;read previous delay
mulx rt ;multiply by reverb time coefficient
rdax iapout,1 ;read left input from input allpass filter bank
rda ap1#,klap ;do an allpass filter
wrap ap1,-klap
rda ap1b#,klap ;do second all pass filter
wrap ap1b,-klap
wrax temp,1 ;write to temp, keep in acc
rdfx lpf1,kfl ;low pass filter
wrlx lpf1,-1
rdfx hpf1,kfh ;high pass filter
wrhx hpf1,-1
rdax temp,-1
mulx pot2 ;crossfade between filter and no filter
rdax temp,1
wra del1,0 ;write to next delay, clear accumulator

;aps into delay2:

rda del1#,1
mulx rt
rda ap2#,klap
wrap ap2,-klap
rda ap2b#,klap
wrap ap2b,-klap
wrax temp,1
rdfx lpf2,kfl
wrlx lpf2,-1
rdfx hpf2,kfh
wrhx hpf2,-1
rdax temp,-1
mulx pot2
rdax temp,1
wra del2,0

;aps into delay3:

rda del2#,1
mulx rt
rdax iapout,1
rda ap3#,klap
wrap ap3,-klap
rda ap3b#,klap
wrap ap3b,-klap
wrax temp,1
rdfx lpf3,kfl
wrlx lpf3,-1
rdfx hpf3,kfh
wrhx hpf3,-1
rdax temp,-1
mulx pot2
rdax temp,1
wra del3,0

;aps into delay4:

rda del3#,1.0
mulx rt
rda ap4#,klap
wrap ap4,-klap
rda ap4b#,klap
wrap ap4b,-klap
wrax temp,1
rdfx lpf4,kfl
wrlx lpf4,-1
rdfx hpf4,kfh
wrhx hpf4,-1
rdax temp,-1
mulx pot2
rdax temp,1
wra del4,0

;take outputs as taps from reverb ring:

rda del2,0.8
rda del3+2876,1.5
rda del1+2093,1.1
wrax dacl,0 ;write output, clear accumulator

rda del1,0.8
rda del3+2876,1.5
rda del4+1234,1.1
wrax dacr,0

;set up lfo, 1Hz to 2Hz, +/-100 samples, for smearing loop all passes:

skp run,2
wlds sin0,30,50
wlds sin1,41,50

;smear 4 allpass filters in reverb ring:

cho rda,sin0,reg|compc,ap1+50 ;sin0
cho rda,sin0,0,ap1+51
wra ap1+100,0

cho rda,sin0,cos|compc,ap2+50 ;cos0
cho rda,sin0,cos,ap2+51
wra ap2+100,0

cho rda,sin1,reg|compc,ap3+50 ;sin1
cho rda,sin1,0,ap3+51
wra ap3+100,0

cho rda,sin1,cos|compc,ap4+50 ;cos1
cho rda,sin1,cos,ap4+51
wra ap4+100,0
Digital Larry
Posts: 338
Joined: Mon Nov 12, 2012 1:12 pm
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Post by Digital Larry »

OK, to summarize, this algorithm is "wet only". The two inputs are mixed together and sent into a single reverb structure. The stereo outputs are created by taking taps from different places within the reverb structure, which in my limited experience does a fairly good job of making it seem like the left and right reverb outs are different.

What is it about this arrangement that you would like to change in order to make it "true stereo"? If you want completely separate reverb structures for left and right, then significant tradeoffs will need to be made and this is not a trivial task.
gkaiomenos
Posts: 19
Joined: Thu Oct 16, 2014 11:59 am

Post by gkaiomenos »

Well the outputs are not so different like for example in the ROM reverb algorithms where you can clearly hear a significant audible difference between left and right outputs.

I don't want to change the overall sound cause i love it so i wasn't thinking of completely separate reverb structures.
Digital Larry
Posts: 338
Joined: Mon Nov 12, 2012 1:12 pm
Contact:

Post by Digital Larry »

OK. I looked a little closer.

Code: Select all

take outputs as taps from reverb ring:

rda del2,0.8
rda del3+2876,1.5
rda del1+2093,1.1
wrax dacl,0 ;write output, clear accumulator

rda del1,0.8
rda del3+2876,1.5
rda del4+1234,1.1
wrax dacr,0 
These are setting the tap points within the structure. Top group is for left output and bottom for right.

The dominant tap in both is actually identical.

Code: Select all

rda del3+2876,1.5
Mess with these values a bit (both the offset and gains) in both blocks. E.g. in the above line the offset is 2876 and the gain is 1.5. I don't have a specific formula other than to suggest looking at other algorithms because many of them use the same 4-delay line structure. Also, make sure the offset is not longer than the corresponding delay line itself:

Code: Select all

mem del1 3559
mem del2 2945
mem del3 3976
mem del4 4445 
This helpful?

DL
gkaiomenos
Posts: 19
Joined: Thu Oct 16, 2014 11:59 am

Post by gkaiomenos »

Wow Thank you Larry
Will try that and get back to you
Cheers
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