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NAMM 2017
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Post new topic   Reply to topic    Spin Semiconductor Forum Index -> FV-1 hardware questions
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skajam66



Joined: 10 Jun 2013
Posts: 13

PostPosted: Sun Apr 02, 2017 7:42 am    Post subject: Reply with quote

Hi,

For the new chip, do you have a target for power consumption?

Ac
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frank



Joined: 19 Oct 2005
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PostPosted: Mon Apr 03, 2017 9:40 am    Post subject: Reply with quote

skajam66 wrote:

For the new chip, do you have a target for power consumption?


Not yet, we are making changes to the chip, some will affect the power consumption. Core does run faster and higher clock rates mean more power.
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dtech



Joined: 11 Apr 2011
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Location: Latvia

PostPosted: Tue Apr 25, 2017 7:58 am    Post subject: Reply with quote

Surprised and excited to see a new chip coming!

Looks very interesting! Finaly it seems capable of synchronised ganging of several dsps, and daisy chaining digital audio buses in between them. I assume 12MHz clock may mean now will be 256 instructions/sample. And linear RAM (though still not 20bit, and still somewhat tiny) is great! I suppose that larger amount of full bitwidth registers will somewhat compensate for the 16bit sram in regards to creating larger filterbanks.

One thing that I wonder - will it allow live WCS modification/update via ic bus? Even very slow "classic" update of one program word per sample would be sufficient for more complex editing and tailoring of things.
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frank



Joined: 19 Oct 2005
Posts: 972

PostPosted: Tue Apr 25, 2017 12:51 pm    Post subject: Reply with quote

dtech wrote:
Finaly it seems capable of synchronised ganging of several dsps, and daisy chaining digital audio buses in between them.


Yes, that is the intent of the 2 I2S buses and the master/slave option.

dtech wrote:
I assume 12MHz clock may mean now will be 256 instructions/sample.


Not exactly, to get maximum performance we went away from the 1 clock per instruction model to a multi-clock model since reading SRAM takes longer than using one of the 8 core registers. As a result you will get more instruction per sample period but the exact number can vary depending on the mix of code. We are estimating about 400 per sample period on average.

dtech wrote:
And linear RAM (though still not 20bit, and still somewhat tiny) is great! I suppose that larger amount of full bitwidth registers will somewhat compensate for the 16bit sram in regards to creating larger filterbanks.


You can address the RAM as linear or use the circular buffer method, each program should only do one method since when using circular it will still go over the entire RAM block. And yes, the big bank of 32-bit registers is intended for filters where you need the resolution though you can really use them for anything.

dtech wrote:
One thing that I wonder - will it allow live WCS modification/update via ic bus? Even very slow "classic" update of one program word per sample would be sufficient for more complex editing and tailoring of things.


No, it is not designed for this. You can only write EEPROM so many times before it will have problems so we would suggest using either the 2nd I2S bus to send coefficients (you will be able to do register*register multiplies at full 32-bit resolution) or use the switch inputs to select from preset coefficients via jumps in the code. Also writing to the EEPROM must be done in blocks and cannot be interrupted so attempting to update single instructions on the fly is not possible.
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seancostello



Joined: 11 Sep 2006
Posts: 74

PostPosted: Thu Jul 06, 2017 1:01 pm    Post subject: Reply with quote

Any more news on the new DSP?
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frank



Joined: 19 Oct 2005
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PostPosted: Fri Jul 07, 2017 9:31 am    Post subject: Reply with quote

Still moving forward, assembler being written, small changes to the instruction set from the one shown at NAMM, etc.
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ice-nine



Joined: 24 May 2012
Posts: 125

PostPosted: Sun Jul 09, 2017 9:27 am    Post subject: Reply with quote

Hi Frank, great to hear things are progressing with the new DSP. Will there be similar support for this DSP as the FV-1 has ? ie Open forum support and programming examples etc.
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frank



Joined: 19 Oct 2005
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PostPosted: Sun Jul 09, 2017 12:27 pm    Post subject: Reply with quote

Yes, the forum will be at the Experimental Noize site and there will be code examples, the assembler will be a free d/l, there will be a dev board, the method to write programs to a chip will be documented so you can do it yourself and not need the dev board or can do it in circuit in your product, etc.
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Mcfly



Joined: 08 Mar 2013
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Location: Argentina

PostPosted: Sun Jul 09, 2017 6:14 pm    Post subject: Reply with quote

Frank, are you planning on discontinuining the fv1?
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frank



Joined: 19 Oct 2005
Posts: 972

PostPosted: Mon Jul 10, 2017 8:08 am    Post subject: Reply with quote

No. The FV-1 is a Spin chip and the FXCore is an EN chip. Chips are targeted at slightly different market segments, the FV-1 is a great, all-in-one chip for basic effects and is in full production. FXCore is being designed to address some areas that FV-1 cannot do (higher resolution math, more POT inputs, etc.) so we need both in the market, you will just decide which one you need in any given product. FXCore will be a more expensive solution since it requires external CODECS but this allows you to select a high end CODEC for a high end product or a low end CODEC for a more affordable product.

Keep designing with the FV-1, it is in full production and there are many new products using it.
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Frank Thomson
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Mcfly



Joined: 08 Mar 2013
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Location: Argentina

PostPosted: Tue Jul 11, 2017 6:40 am    Post subject: Reply with quote

frank wrote:
No. The FV-1 is a Spin chip and the FXCore is an EN chip. Chips are targeted at slightly different market segments, the FV-1 is a great, all-in-one chip for basic effects and is in full production. FXCore is being designed to address some areas that FV-1 cannot do (higher resolution math, more POT inputs, etc.) so we need both in the market, you will just decide which one you need in any given product. FXCore will be a more expensive solution since it requires external CODECS but this allows you to select a high end CODEC for a high end product or a low end CODEC for a more affordable product.

Keep designing with the FV-1, it is in full production and there are many new products using it.


Great to hear that!
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seancostello



Joined: 11 Sep 2006
Posts: 74

PostPosted: Tue Jul 18, 2017 10:22 am    Post subject: Reply with quote

Will the FXCore run at sampling rates other than 48 kHz?
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frank



Joined: 19 Oct 2005
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PostPosted: Thu Jul 20, 2017 7:36 am    Post subject: Reply with quote

seancostello wrote:
Will the FXCore run at sampling rates other than 48 kHz?

Yes it will
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igorp



Joined: 19 May 2015
Posts: 12

PostPosted: Thu Aug 31, 2017 4:18 am    Post subject: Reply with quote

Have it build in ADCs and DACs? or FXCore need external codec?
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frank



Joined: 19 Oct 2005
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PostPosted: Thu Aug 31, 2017 12:00 pm    Post subject: Reply with quote

External CODEC, allows you to select the quality/cost trade off on a per product basis.
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