Spin Semiconductor Forum Index Spin Semiconductor
Support forum
 
 FAQFAQ   SearchSearch   MemberlistMemberlist   UsergroupsUsergroups   RegisterRegister 
 ProfileProfile   Log in to check your private messagesLog in to check your private messages   Log inLog in 

That 8-second delay patch

 
Post new topic   Reply to topic    Spin Semiconductor Forum Index -> Algorithm development
View previous topic :: View next topic  
Author Message
Digital Larry



Joined: 12 Nov 2012
Posts: 274

PostPosted: Tue Jul 04, 2017 6:41 am    Post subject: That 8-second delay patch Reply with quote

http://www.spinsemi.com/forum/viewtopic.php?t=418

I finally tried this one out, and at least for ME:

1) The code as presented actually generates a 9-second delay at 32 kHz.
2) Attempts to change the sampling divisor are a little strange. here's the section of code where you'd think you could adjust this to your heart's content:

Code:
; Add 0.1 to the loop counter.
ldax   loop
sof   1, 0.1
wrax   loop, 1
; IF loop counter is > 0.8, THEN write the temp variable to the output, and reset loop variable to 0
sof   1, -0.8
skp   neg, Done
ldax   temp
wrax   output, 0
wrax   loop, 0
Done:


I'm not at my dev board, so this may be a little off, but using -0.8 gives 9 seconds. I was able to change this value to get different delay lengths, but I could only get 1, 3, 5, 7, 9. I couldn't get any even numbered delay multipliers. Now that really baffled me as I figured hey we're just adding one thing and subtracting another thing and seeing if the result is negative.

So then I thought maybe this is due to quantization, that we are getting some rounding errors and it is putting the values off ever so slightly. So I tried using -0.79 or -0.81 but that didn't help.

Anyone messed with this code to give a 2:1 delay multiplier? That's what I'm really after. It doesn't have to be adjustable. With this code, and the small amount of time I spent, I could get 1 or 3 but not 2.
Back to top
View user's profile Send private message Visit poster's website
frank



Joined: 19 Oct 2005
Posts: 972

PostPosted: Tue Jul 04, 2017 11:09 am    Post subject: Reply with quote

I think the reason you are only getting odd odd number multiples is the interleaving of the samples in delay memory. Set the delay length to an odd number for an even multiple. Note I have not tried this but here is my thinking:

We are skipping samples saving/reading to/from delay memory, if we have an even number of memory locations and an odd multiple then the pattern is (assuming 10 sample delay and a x3 multiple):
0, 3, 6, 9, 2, 5, 8, 1, 4, 7, 0, 3, 6, ...

But for an even multiple like 2:
0, 2, 4, 6, 8, 0, 2, 4, ...

we never use the odd sample memory locations so we want an odd number of samples like 11 and then we get:
0, 2, 4, 8, 10, 1, 3, 5, 7, 9, 0, 2, ...

So try changing the write/read points by 1 and see what happens.
_________________
Frank Thomson
Experimental Noize
Back to top
View user's profile Send private message Visit poster's website
Display posts from previous:   
Post new topic   Reply to topic    Spin Semiconductor Forum Index -> Algorithm development All times are GMT - 8 Hours
Page 1 of 1

 
Jump to:  
You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot vote in polls in this forum


Powered by phpBB © 2001, 2005 phpBB Group