I try to understand the single delay bloc code from SpinCAD Designer. I already read all the FV-1 Datasheet, AN0001..
I understood that to get a delay effect we need to but a sample at the beginning of a delay line (= portion of the delay ram ?) and then read at another adress in the delay ram so the time if the repeats is related to the adress we read.
But there still some things I don't get/I'm not sure if it's working like I think it really is:
- Is each spinasm code running in a kind of infinite loop ? (if I understood the code we write is only for 1 audio sample )
- How the sample is moving into the delay ram ?
- Why are we writing the sample + all the ACC in the adress 0 of the delay ram and not just writing the sample itself ?
- How the repeats are created ?
- Are the 'lines which are useless to me' really useless ? (I tried to delet them and it still works so I assume these are automatically SpinCAD generated code lines to prevent that the ACC is really empty before doing some operations)
- If I want to get a 1000 ms delay can I just replace the lines 5 and 6 by SOF 0.0,1.0 ? What the point of having 2 lines here since we could just directly write SOF 0.0,0.25 ?
Here's the code with my comments.
Code: Select all
;Delay Analysis
;These two lines are useless
RDAX ADCL,0.5000000000 ;1 Read left ADC and put the half of the sample into the ACC
WRAX REG1,0.0000000000 ;2 Write the value of ACC into REG1 and clear the ACC
SOF 0.0000000000,0.4500000000 ;3 Put 0.45 into the ACC
WRAX REG1,0.0000000000 ;4 Write the value of ACC into REG1 and clear ACC
SOF 0.0000000000,0.9990000000 ;5 Put 0.999 into ACC
SOF 0.2500000000,0.0000305176 ;6 ACC*0.25 + 0.0000305176
WRAX ADDR_PTR,0.0000000000 ;7 Write ACC into ADDR_PTR and clear ACC
RMPA 1.0 ;8 Read from the RAM (so RAMADDRESS = ADDR_PTR, (so the value of ADDR_PTR contain the time since we're reading at this adress),
;multiply the value by C (if C>1 we start to have self oscillation of the delay)
WRAX REG0,1.0000000000 ;9 write ACC into REG0 and keep the value into ACC too
MULX REG1 ;10 Multiply ACC with REG1 value and put the result into ACC
RDAX ADCL,0.5000000000 ;11 Read left ADC and put the half of the sample into the ACC and add it with the old ACC value
WRA 0,0.0 ;12 Write ACC into the RAM at the @0 and clear ACC
;These two lines are useless
RDAX REG0,1.0000000000 ;13 Put REG0 value into ACC and keep ACC value
WRAX REG0,0.0000000000 ;14 Write REG0 value into ACC and clear ACC
;------ Output
RDAX REG0,1.0000000000 ;15 Read REG0 value and put it into ACC
WRAX DACR,0.0000000000 ;16 Write ACC into right channel DAC and clear ACC
I have already some knowledge in uP, uC and programing but it's the first time for me with DSP stuff so if you know any good books which can help me to understand how the delay ram is working I would be really interested!
Thanks