Synchronizing two FV-1
Moderator: frank
Synchronizing two FV-1
Supposing we have two FV-1 clocked by a common crystal external oscillator, is there a way two synchronise them, that is sharing a common start point such that the programs in both FV-1 can be executed in sync ?
Yves - yusynth
Re: Synchronizing two FV-1
Short answer is no, there is no way to guarantee it. Program changes should happen within one sample clock, actual execution should be within one instruction period if both are driven with the same external clock.
Frank Thomson
Experimental Noize
Experimental Noize
Re: Synchronizing two FV-1
OK, correct me if I am wrong, but if they share the same clock, considering the two FV-1 are set on the same external program and powered by the same supply, would the maximum de-synchronisation between the execution start points of each FV-1 be less than say ten sample steps (10/32768 s)? If so it is OK for me.
Yves - yusynth
Re: Synchronizing two FV-1
There are many places for skews to occur in the chip due to board layout, normal fab process variation, etc. So what can happen is:
Chips exit reset at different times. Shouldn't be more than a few samples but there is no spec for this so we cannot guarantee it would be less than 10 samples.
Due to PCB variations the chips see slightly skewed sample clocks. Keep paths from oscillator to FV-1s the same length.
Internal skewing due to process variations. This should be MUCH less than one instruction clock.
Due to possible skew in the internal clocks it is possible, based on when a user changes a program relative to pin sampling, that one chip sees the change before the other so there is a sample difference between program changes. Note that PCB layout can also effect this so again keep trace lengths from switch to FV-1s the same.
So start up is the biggest unknown, once both chips are up and running the possible skew (assuming trace lengths are carefully controlled) should be one sample clock on program change and much less than one instruction clock on actual instruction execution.
Chips exit reset at different times. Shouldn't be more than a few samples but there is no spec for this so we cannot guarantee it would be less than 10 samples.
Due to PCB variations the chips see slightly skewed sample clocks. Keep paths from oscillator to FV-1s the same length.
Internal skewing due to process variations. This should be MUCH less than one instruction clock.
Due to possible skew in the internal clocks it is possible, based on when a user changes a program relative to pin sampling, that one chip sees the change before the other so there is a sample difference between program changes. Note that PCB layout can also effect this so again keep trace lengths from switch to FV-1s the same.
So start up is the biggest unknown, once both chips are up and running the possible skew (assuming trace lengths are carefully controlled) should be one sample clock on program change and much less than one instruction clock on actual instruction execution.
Frank Thomson
Experimental Noize
Experimental Noize
Re: Synchronizing two FV-1s
Thanks very much for all these information.
I will then try to prototype a PCB with special care on the track length from the clock to the FV-1s and to the PSU.
I will then try to prototype a PCB with special care on the track length from the clock to the FV-1s and to the PSU.
Yves - yusynth
Re: Synchronizing two FV-1s
Hi Yves nice to see you here
are you gonna publish your upcoming spin FV-1 board on Yusynth site
cheers
Re: Synchronizing two FV-1
I made a PCB that I might publish, and may be some algorithms, but not sure about it yet.
Yves - yusynth