Spin Semiconductor

Posted: **Mon May 13, 2019 8:30 pm**

Hello!
I'm trying to add some minor changes to 3k_hall preset.

Here is original code:

;Hall.

;Pot0 = predelay 0-100ms.
;Pot1 = reverb time
;Pot2 = damping

mem	pdel	3277	;100ms predelay space

mem	idel	8000	;initial sound space

mem	iap0	31
mem	iap1	47
mem	iap2	73
mem	iap3	171
mem	iap4	196
mem	iap5	371
mem	iap6	496	;thickening all passes imbeded in intial delay

mem	ap1	234
mem	ap2	356
mem	ap3	962
mem	ap4	1263	;reverb loop input all passes

mem	lap1a	1921
mem	lap1b	2645
mem	d1	3534
mem	lap2a	2294
mem	lap2b	2767
mem	d2	3745	;loop constants

;write-first registers:

equ	kirt	reg0	;coefficint to scale initial sound
equ	krt	reg1	;coefficient to affect RT of loop
equ	apout	reg2	;output of loop input all passes
equ	kd	reg3	;damping coefficient (for shelving)
equ	temp	reg4	;temp register for filter routines
equ	gain	reg5	;adjust gain with RT

;read-first registers:

equ	lf1	reg20	;reverb loop filter 1
equ	lf2	reg21	;reverb loop filter 2
equ	hf1	reg22	;loop high pass 1 (fixed)
equ	hf2	reg23	;loop high pass 2 (fixed)
equ	lfin2	reg25	;LPF for imbedding in intial delay
equ	lf	reg26	;input low pass (shelving with kd)

;clear read-first registers, setup lfo:

skp	run,endclr
wrax	lf1,0
wrax	lf2,0
wrax	hf1,0
wrax	hf2,0
wrax	lfin2,0
wlds	sin0,20,100
endclr:

;initial sound tap positions (30.5uS/location, 100=3.05mS):

equ	ld1	2074	;first tap, left
equ	rd1	2174	;first tap, right
equ	ld2	3556	;and so on...
equ	rd2	3962
equ	ld3	3345
equ	rd3	3121
equ	ld4	3656
equ	rd4	3453
equ	ld5	5121
equ	rd5	5624
equ	ld6	6579
equ	rd6	7940

;prepare predelay pot:

rdax	pot0,0.1		;to 1/10th total delay (100ms)
and	%01111110_00000000_00000000
wrax	addr_ptr,0		;write to memory pointer

;prepare decay pot:

rdax	pot1,0.97		;get pot, limit to less than infinite
wrax	krt,1			;write loop decay time
sof	0.4,0.6			;scale to 0.6 to 1.0
wrax	kirt,0			;write impulse filter gains
sof	-1,0.99			;scale to decrease gain with RT
wrax	gain,0			;write gain factor

;prepare damping pot:

rdax	pot2,-1
wrax	kd,0			;increases shelf to -1 (infinite loss)

;do inputs to predelay:

rdax	adcl,0.5
rdax	adcr,0.5		;get inputs
mulx	gain			;give greater gain to short RT 
wra	pdel,0

;read predelay and write initial response delay:

rmpa	1
rda	iap0#,0.5
wrap	iap0,-0.5		;complicate input to initial delay
wrax	temp,1
rdfx	lf,0.4
wrhx	lf,-1
mulx	kd
rdax	temp,1			;low pass fiter entire input
wra	idel,0			;write initial sound delay

;complicate initial sound:

rda	idel+500,1
rda	iap1#,0.5
wrap	iap1,-0.5
wra	idel+500,0

rda	idel+1000,1
rda	iap2#,0.5
wrap	iap2,-0.5
wra	idel+1000,0

rda	idel+1500,1
rda	iap3#,0.5
wrap	iap3,-0.5
wra	idel+1500,0

rda	idel+2000,1
rda	iap4#,0.5
wrap	iap4,-0.5
wra	idel+2000,0

rda	idel+2500,1
rda	iap5#,0.5
wrap	iap5,-0.5
wrax	temp,1			;save filter input
rdfx	lfin2,0.3
wrhx	lfin2,-1		;make HP filter
mulx	kd			;multiply by negative shelving coef
rdax	temp,1			;add back input (shelving LPF)
wra	idel+2500,0

rda	idel+3000,1
rda	iap6#,0.5
wrap	iap6,-0.5
wra	idel+3000,0

;do reverb input all passes:

rda	idel,1
rda	ap1#,0.5
wrap	ap1,-0.5
rda	ap2#,0.5
wrap	ap2,-0.5
rda	ap3#,0.5
wrap	ap3,-0.5
rda	ap4#,0.5
wrap	ap4,-0.5
wrax	apout,0

;do reverb loop and sum all outputs:

rda	d2#,1
mulx	krt
rdax	apout,1
rda	lap1a#,0.5
wrap	lap1a,-0.5
rda	lap1b#,0.5
wrap	lap1b,-0.5
wrax	temp,1			;save filter input
rdfx	lf1,0.4
wrhx	lf1,-1			;make HP filter
mulx	kd			;multiply by negative shelving coef
rdax	temp,1			;add back input (shelving LPF)
rdfx	hf1,0.005
wrhx	hf1,-0.5		;roll out lows in loop
wra	d1,1.99

rda	idel+ld6,-0.5
mulx	kirt
rda	idel+ld5,0.7
mulx	kirt
rda	idel+ld4,0.6
mulx	kirt
rda	idel+ld3,0.5
mulx	kirt
rda	idel+ld2,0.6
rda	idel+ld1,-0.6
wrax	dacl,0

rda	d1#,1
mulx	krt
rdax	apout,1
rda	lap2a#,0.5
wrap	lap2a,-0.5
rda	lap2b#,0.5
wrap	lap2b,-0.5
wrax	temp,1			
rdfx	lf2,0.4
wrhx	lf2,-1			
mulx	kd			
rdax	temp,1	
rdfx	hf2,0.005
wrhx	hf2,-0.5				
wra	d2,1.99

rda	idel+rd6,0.6
mulx	kirt
rda	idel+rd5,-0.5
mulx	kirt
rda	idel+rd4,0.6
mulx	kirt
rda	idel+rd3,0.5
mulx	kirt
rda	idel+rd2,-0.6
rda	idel+rd1,0.5
wrax	dacr,0

;do delay smoothing:

cho	rda,sin0,sin|reg|compc,d1+100
cho	rda,sin0,sin,d1+101
wra	d1+200,0

cho	rda,sin0,cos|reg|compc,d1+100
cho	rda,sin0,cos,d1+101
wra	d1+200,0

I needed to change pots assigment due to my schematick, I've chaged whithin "search and replace", code worked well, here is modifyed code:

Code: Select all

;Hall.

;pot2 = predelay 0-100ms.
;pot0 = reverb time
;pot1 = damping

mem	pdel	3277	;100ms predelay space

mem	idel	8000	;initial sound space

mem	iap0	31
mem	iap1	47
mem	iap2	73
mem	iap3	171
mem	iap4	196
mem	iap5	371
mem	iap6	496	;thickening all passes imbeded in intial delay

mem	ap1	234
mem	ap2	356
mem	ap3	962
mem	ap4	1263	;reverb loop input all passes

mem	lap1a	1921
mem	lap1b	2645
mem	d1	3534
mem	lap2a	2294
mem	lap2b	2767
mem	d2	3745	;loop constants

;write-first registers:

equ	kirt	reg0	;coefficint to scale initial sound
equ	krt	reg1	;coefficient to affect RT of loop
equ	apout	reg2	;output of loop input all passes
equ	kd	reg3	;damping coefficient (for shelving)
equ	temp	reg4	;temp register for filter routines
equ	gain	reg5	;adjust gain with RT

;read-first registers:

equ	lf1	reg20	;reverb loop filter 1
equ	lf2	reg21	;reverb loop filter 2
equ	hf1	reg22	;loop high pass 1 (fixed)
equ	hf2	reg23	;loop high pass 2 (fixed)
equ	lfin2	reg25	;LPF for imbedding in intial delay
equ	lf	reg26	;input low pass (shelving with kd)

;clear read-first registers, setup lfo:

skp	run,endclr
wrax	lf1,0
wrax	lf2,0
wrax	hf1,0
wrax	hf2,0
wrax	lfin2,0
wlds	sin0,20,100
endclr:

;initial sound tap positions (30.5uS/location, 100=3.05mS):

equ	ld1	2074	;first tap, left
equ	rd1	2174	;first tap, right
equ	ld2	3556	;and so on...
equ	rd2	3962
equ	ld3	3345
equ	rd3	3121
equ	ld4	3656
equ	rd4	3453
equ	ld5	5121
equ	rd5	5624
equ	ld6	6579
equ	rd6	7940

;prepare predelay pot:

rdax	pot2,0.1		;to 1/10th total delay (100ms)
and	%01111110_00000000_00000000
wrax	addr_ptr,0		;write to memory pointer

;prepare decay pot:

rdax	pot0,0.97		;get pot, limit to less than infinite
wrax	krt,1			;write loop decay time
sof	0.4,0.6			;scale to 0.6 to 1.0
wrax	kirt,0			;write impulse filter gains
sof	-1,0.99			;scale to decrease gain with RT
wrax	gain,0			;write gain factor

;prepare damping pot:

rdax	pot1,-1
wrax	kd,0			;increases shelf to -1 (infinite loss)

;do inputs to predelay:

rdax	adcl,0.5
rdax	adcr,0.5		;get inputs
mulx	gain			;give greater gain to short RT 
wra	pdel,0

;read predelay and write initial response delay:

rmpa	1
rda	iap0#,0.5
wrap	iap0,-0.5		;complicate input to initial delay
wrax	temp,1
rdfx	lf,0.4
wrhx	lf,-1
mulx	kd
rdax	temp,1			;low pass fiter entire input
wra	idel,0			;write initial sound delay

;complicate initial sound:

rda	idel+500,1
rda	iap1#,0.5
wrap	iap1,-0.5
wra	idel+500,0

rda	idel+1000,1
rda	iap2#,0.5
wrap	iap2,-0.5
wra	idel+1000,0

rda	idel+1500,1
rda	iap3#,0.5
wrap	iap3,-0.5
wra	idel+1500,0

rda	idel+2000,1
rda	iap4#,0.5
wrap	iap4,-0.5
wra	idel+2000,0

rda	idel+2500,1
rda	iap5#,0.5
wrap	iap5,-0.5
wrax	temp,1			;save filter input
rdfx	lfin2,0.3
wrhx	lfin2,-1		;make HP filter
mulx	kd			;multiply by negative shelving coef
rdax	temp,1			;add back input (shelving LPF)
wra	idel+2500,0

rda	idel+3000,1
rda	iap6#,0.5
wrap	iap6,-0.5
wra	idel+3000,0

;do reverb input all passes:

rda	idel,1
rda	ap1#,0.5
wrap	ap1,-0.5
rda	ap2#,0.5
wrap	ap2,-0.5
rda	ap3#,0.5
wrap	ap3,-0.5
rda	ap4#,0.5
wrap	ap4,-0.5
wrax	apout,0

;do reverb loop and sum all outputs:

rda	d2#,1
mulx	krt
rdax	apout,1
rda	lap1a#,0.5
wrap	lap1a,-0.5
rda	lap1b#,0.5
wrap	lap1b,-0.5
wrax	temp,1			;save filter input
rdfx	lf1,0.4
wrhx	lf1,-1			;make HP filter
mulx	kd			;multiply by negative shelving coef
rdax	temp,1			;add back input (shelving LPF)
rdfx	hf1,0.005
wrhx	hf1,-0.5		;roll out lows in loop
wra	d1,1.99

rda	idel+ld6,-0.5
mulx	kirt
rda	idel+ld5,0.7
mulx	kirt
rda	idel+ld4,0.6
mulx	kirt
rda	idel+ld3,0.5
mulx	kirt
rda	idel+ld2,0.6
rda	idel+ld1,-0.6
wrax	dacl,0

rda	d1#,1
mulx	krt
rdax	apout,1
rda	lap2a#,0.5
wrap	lap2a,-0.5
rda	lap2b#,0.5
wrap	lap2b,-0.5
wrax	temp,1			
rdfx	lf2,0.4
wrhx	lf2,-1			
mulx	kd			
rdax	temp,1	
rdfx	hf2,0.005
wrhx	hf2,-0.5				
wra	d2,1.99

rda	idel+rd6,0.6
mulx	kirt
rda	idel+rd5,-0.5
mulx	kirt
rda	idel+rd4,0.6
mulx	kirt
rda	idel+rd3,0.5
mulx	kirt
rda	idel+rd2,-0.6
rda	idel+rd1,0.5
wrax	dacr,0

;do delay smoothing:

cho	rda,sin0,sin|reg|compc,d1+100
cho	rda,sin0,sin,d1+101
wra	d1+200,0

cho	rda,sin0,cos|reg|compc,d1+100
cho	rda,sin0,cos,d1+101
wra	d1+200,0

After that I've figure out that i need to reverse pot1, I've find such code for that: sof -1,0.999, and I've added it in line 93, here is problem code:

Code: Select all

;Hall.

;pot2 = predelay 0-100ms.
;pot0 = reverb time
;pot1 = damping

mem	pdel	3277	;100ms predelay space

mem	idel	8000	;initial sound space

mem	iap0	31
mem	iap1	47
mem	iap2	73
mem	iap3	171
mem	iap4	196
mem	iap5	371
mem	iap6	496	;thickening all passes imbeded in intial delay

mem	ap1	234
mem	ap2	356
mem	ap3	962
mem	ap4	1263	;reverb loop input all passes

mem	lap1a	1921
mem	lap1b	2645
mem	d1	3534
mem	lap2a	2294
mem	lap2b	2767
mem	d2	3745	;loop constants

;write-first registers:

equ	kirt	reg0	;coefficint to scale initial sound
equ	krt	reg1	;coefficient to affect RT of loop
equ	apout	reg2	;output of loop input all passes
equ	kd	reg3	;damping coefficient (for shelving)
equ	temp	reg4	;temp register for filter routines
equ	gain	reg5	;adjust gain with RT

;read-first registers:

equ	lf1	reg20	;reverb loop filter 1
equ	lf2	reg21	;reverb loop filter 2
equ	hf1	reg22	;loop high pass 1 (fixed)
equ	hf2	reg23	;loop high pass 2 (fixed)
equ	lfin2	reg25	;LPF for imbedding in intial delay
equ	lf	reg26	;input low pass (shelving with kd)

;clear read-first registers, setup lfo:

skp	run,endclr
wrax	lf1,0
wrax	lf2,0
wrax	hf1,0
wrax	hf2,0
wrax	lfin2,0
wlds	sin0,20,100
endclr:

;initial sound tap positions (30.5uS/location, 100=3.05mS):

equ	ld1	2074	;first tap, left
equ	rd1	2174	;first tap, right
equ	ld2	3556	;and so on...
equ	rd2	3962
equ	ld3	3345
equ	rd3	3121
equ	ld4	3656
equ	rd4	3453
equ	ld5	5121
equ	rd5	5624
equ	ld6	6579
equ	rd6	7940

;prepare predelay pot:

rdax	pot2,0.1		;to 1/10th total delay (100ms)
and	%01111110_00000000_00000000
wrax	addr_ptr,0		;write to memory pointer

;prepare decay pot:

rdax	pot0,0.97		;get pot, limit to less than infinite
wrax	krt,1			;write loop decay time
sof	0.4,0.6			;scale to 0.6 to 1.0
wrax	kirt,0			;write impulse filter gains
sof	-1,0.99			;scale to decrease gain with RT
wrax	gain,0			;write gain factor

;prepare damping pot:

rdax	pot1,-1
sof	-1,0.999															;line 93, problem 
wrax	kd,0			;increases shelf to -1 (infinite loss)

;do inputs to predelay:

rdax	adcl,0.5
rdax	adcr,0.5		;get inputs
mulx	gain			;give greater gain to short RT 
wra	pdel,0

;read predelay and write initial response delay:

rmpa	1
rda	iap0#,0.5
wrap	iap0,-0.5		;complicate input to initial delay
wrax	temp,1
rdfx	lf,0.4
wrhx	lf,-1
mulx	kd
rdax	temp,1			;low pass fiter entire input
wra	idel,0			;write initial sound delay

;complicate initial sound:

rda	idel+500,1
rda	iap1#,0.5
wrap	iap1,-0.5
wra	idel+500,0

rda	idel+1000,1
rda	iap2#,0.5
wrap	iap2,-0.5
wra	idel+1000,0

rda	idel+1500,1
rda	iap3#,0.5
wrap	iap3,-0.5
wra	idel+1500,0

rda	idel+2000,1
rda	iap4#,0.5
wrap	iap4,-0.5
wra	idel+2000,0

rda	idel+2500,1
rda	iap5#,0.5
wrap	iap5,-0.5
wrax	temp,1			;save filter input
rdfx	lfin2,0.3
wrhx	lfin2,-1		;make HP filter
mulx	kd			;multiply by negative shelving coef
rdax	temp,1			;add back input (shelving LPF)
wra	idel+2500,0

rda	idel+3000,1
rda	iap6#,0.5
wrap	iap6,-0.5
wra	idel+3000,0

;do reverb input all passes:

rda	idel,1
rda	ap1#,0.5
wrap	ap1,-0.5
rda	ap2#,0.5
wrap	ap2,-0.5
rda	ap3#,0.5
wrap	ap3,-0.5
rda	ap4#,0.5
wrap	ap4,-0.5
wrax	apout,0

;do reverb loop and sum all outputs:

rda	d2#,1
mulx	krt
rdax	apout,1
rda	lap1a#,0.5
wrap	lap1a,-0.5
rda	lap1b#,0.5
wrap	lap1b,-0.5
wrax	temp,1			;save filter input
rdfx	lf1,0.4
wrhx	lf1,-1			;make HP filter
mulx	kd			;multiply by negative shelving coef
rdax	temp,1			;add back input (shelving LPF)
rdfx	hf1,0.005
wrhx	hf1,-0.5		;roll out lows in loop
wra	d1,1.99

rda	idel+ld6,-0.5
mulx	kirt
rda	idel+ld5,0.7
mulx	kirt
rda	idel+ld4,0.6
mulx	kirt
rda	idel+ld3,0.5
mulx	kirt
rda	idel+ld2,0.6
rda	idel+ld1,-0.6
wrax	dacl,0

rda	d1#,1
mulx	krt
rdax	apout,1
rda	lap2a#,0.5
wrap	lap2a,-0.5
rda	lap2b#,0.5
wrap	lap2b,-0.5
wrax	temp,1			
rdfx	lf2,0.4
wrhx	lf2,-1			
mulx	kd			
rdax	temp,1	
rdfx	hf2,0.005
wrhx	hf2,-0.5				
wra	d2,1.99

rda	idel+rd6,0.6
mulx	kirt
rda	idel+rd5,-0.5
mulx	kirt
rda	idel+rd4,0.6
mulx	kirt
rda	idel+rd3,0.5
mulx	kirt
rda	idel+rd2,-0.6
rda	idel+rd1,0.5
wrax	dacr,0

;do delay smoothing:

cho	rda,sin0,sin|reg|compc,d1+100
cho	rda,sin0,sin,d1+101
wra	d1+200,0

cho	rda,sin0,cos|reg|compc,d1+100
cho	rda,sin0,cos,d1+101
wra	d1+200,0

And I can't save this code to .hex file, spinAsm showes this error:
<0000>[ Pass 1] [ 1015] Line: 231 "wra d1+200,0 " - ERROR:Program Length Exceeds Limit -
<0001>[ Pass 1] [ 1031] Line: 231 "wra d1+200,0 " - ERROR:FAILED On Pass - ONE

Machine code viewer showes this error:
0007 endclr:

I also have the similar issue in another preset.
So, can someone help my to figure out the reason and solve this problem? Please)

Posted: **Mon May 13, 2019 10:36 pm**

The error "ERROR:Program Length Exceeds Limit " is telling you exactly what the problem is, you are only allowed 128 instructions in a program and you have more than that so you need to cut the program length down.

Posted: **Tue May 14, 2019 1:09 pm**

Thanks for the answer!
Is there any other way to reverse pot without adding new functions? And without soldering iron))
I'm just a beginner in coding, and I don't know what part of code can I delete and how it will effect on sound(

Posted: **Tue May 14, 2019 4:57 pm**

What to do depends on a number of things. This is a stereo output reverb, are you using both outputs? If not then you can delete the summation and output for the unused channel. If you are using both outputs then the easy answer is don't reverse the POT in code do it on the PCB or swap the wires on the POT if not PCB mounted.

Posted: **Wed May 15, 2019 7:14 am**

Thanks for reply!
I'm using mono, so, ive decided to put ";" before line with "dacr" in hall reverb and "adcr,dacr" in plate reverb, here is the code:

hall (changes in line 221):

Code: Select all

;Hall.

;pot2 = predelay 0-100ms.
;pot0 = reverb time
;pot1 = damping

mem	pdel	3277	;100ms predelay space

mem	idel	8000	;initial sound space

mem	iap0	31
mem	iap1	47
mem	iap2	73
mem	iap3	171
mem	iap4	196
mem	iap5	371
mem	iap6	496	;thickening all passes imbeded in intial delay

mem	ap1	234
mem	ap2	356
mem	ap3	962
mem	ap4	1263	;reverb loop input all passes

mem	lap1a	1921
mem	lap1b	2645
mem	d1	3534
mem	lap2a	2294
mem	lap2b	2767
mem	d2	3745	;loop constants

;write-first registers:

equ	kirt	reg0	;coefficint to scale initial sound
equ	krt	reg1	;coefficient to affect RT of loop
equ	apout	reg2	;output of loop input all passes
equ	kd	reg3	;damping coefficient (for shelving)
equ	temp	reg4	;temp register for filter routines
equ	gain	reg5	;adjust gain with RT

;read-first registers:

equ	lf1	reg20	;reverb loop filter 1
equ	lf2	reg21	;reverb loop filter 2
equ	hf1	reg22	;loop high pass 1 (fixed)
equ	hf2	reg23	;loop high pass 2 (fixed)
equ	lfin2	reg25	;LPF for imbedding in intial delay
equ	lf	reg26	;input low pass (shelving with kd)

;clear read-first registers, setup lfo:

skp	run,endclr
wrax	lf1,0
wrax	lf2,0
wrax	hf1,0
wrax	hf2,0
wrax	lfin2,0
wlds	sin0,20,100
endclr:

;initial sound tap positions (30.5uS/location, 100=3.05mS):

equ	ld1	2074	;first tap, left
equ	rd1	2174	;first tap, right
equ	ld2	3556	;and so on...
equ	rd2	3962
equ	ld3	3345
equ	rd3	3121
equ	ld4	3656
equ	rd4	3453
equ	ld5	5121
equ	rd5	5624
equ	ld6	6579
equ	rd6	7940

;prepare predelay pot:

rdax	pot2,0.1		;to 1/10th total delay (100ms)
and	%01111110_00000000_00000000
wrax	addr_ptr,0		;write to memory pointer

;prepare decay pot:

rdax	pot0,0.97		;get pot, limit to less than infinite
wrax	krt,1			;write loop decay time
sof	0.4,0.6			;scale to 0.6 to 1.0
wrax	kirt,0			;write impulse filter gains
sof	-1,0.99			;scale to decrease gain with RT
wrax	gain,0			;write gain factor

;prepare damping pot:

rdax	pot1,-1
sof	-1,0.999
wrax	kd,0			;increases shelf to -1 (infinite loss)

;do inputs to predelay:

rdax	adcl,0.5
rdax	adcr,0.5		;get inputs
mulx	gain			;give greater gain to short RT 
wra	pdel,0

;read predelay and write initial response delay:

rmpa	1
rda	iap0#,0.5
wrap	iap0,-0.5		;complicate input to initial delay
wrax	temp,1
rdfx	lf,0.4
wrhx	lf,-1
mulx	kd
rdax	temp,1			;low pass fiter entire input
wra	idel,0			;write initial sound delay

;complicate initial sound:

rda	idel+500,1
rda	iap1#,0.5
wrap	iap1,-0.5
wra	idel+500,0

rda	idel+1000,1
rda	iap2#,0.5
wrap	iap2,-0.5
wra	idel+1000,0

rda	idel+1500,1
rda	iap3#,0.5
wrap	iap3,-0.5
wra	idel+1500,0

rda	idel+2000,1
rda	iap4#,0.5
wrap	iap4,-0.5
wra	idel+2000,0

rda	idel+2500,1
rda	iap5#,0.5
wrap	iap5,-0.5
wrax	temp,1			;save filter input
rdfx	lfin2,0.3
wrhx	lfin2,-1		;make HP filter
mulx	kd			;multiply by negative shelving coef
rdax	temp,1			;add back input (shelving LPF)
wra	idel+2500,0

rda	idel+3000,1
rda	iap6#,0.5
wrap	iap6,-0.5
wra	idel+3000,0

;do reverb input all passes:

rda	idel,1
rda	ap1#,0.5
wrap	ap1,-0.5
rda	ap2#,0.5
wrap	ap2,-0.5
rda	ap3#,0.5
wrap	ap3,-0.5
rda	ap4#,0.5
wrap	ap4,-0.5
wrax	apout,0

;do reverb loop and sum all outputs:

rda	d2#,1
mulx	krt
rdax	apout,1
rda	lap1a#,0.5
wrap	lap1a,-0.5
rda	lap1b#,0.5
wrap	lap1b,-0.5
wrax	temp,1			;save filter input
rdfx	lf1,0.4
wrhx	lf1,-1			;make HP filter
mulx	kd			;multiply by negative shelving coef
rdax	temp,1			;add back input (shelving LPF)
rdfx	hf1,0.005
wrhx	hf1,-0.5		;roll out lows in loop
wra	d1,1.99

rda	idel+ld6,-0.5
mulx	kirt
rda	idel+ld5,0.7
mulx	kirt
rda	idel+ld4,0.6
mulx	kirt
rda	idel+ld3,0.5
mulx	kirt
rda	idel+ld2,0.6
rda	idel+ld1,-0.6
wrax	dacl,0

rda	d1#,1
mulx	krt
rdax	apout,1
rda	lap2a#,0.5
wrap	lap2a,-0.5
rda	lap2b#,0.5
wrap	lap2b,-0.5
wrax	temp,1			
rdfx	lf2,0.4
wrhx	lf2,-1			
mulx	kd			
rdax	temp,1	
rdfx	hf2,0.005
wrhx	hf2,-0.5				
wra	d2,1.99

rda	idel+rd6,0.6
mulx	kirt
rda	idel+rd5,-0.5
mulx	kirt
rda	idel+rd4,0.6
mulx	kirt
rda	idel+rd3,0.5
mulx	kirt
rda	idel+rd2,-0.6
rda	idel+rd1,0.5
;wrax	dacr,0

;do delay smoothing:

cho	rda,sin0,sin|reg|compc,d1+100
cho	rda,sin0,sin,d1+101
wra	d1+200,0

cho	rda,sin0,cos|reg|compc,d1+100
cho	rda,sin0,cos,d1+101
wra	d1+200,0

Plate (changes in line 95 and 176):

Code: Select all

;Plate program.
 
;pot2 = predelay (0-127)
;pot0 = RT (0-127)
;pot1 = damping (0-127)

mem	pdel	3276

mem	ap1	123
mem	ap2	234
mem	ap3	345
mem	ap4	456

mem	lap1a	567
mem	lap1b	1267
mem	d1	1536
mem	lap2a	468
mem	lap2b	1367
mem	d2	1691
mem	lap3a	678
mem	lap3b	1127
mem	d3	1436
mem	lap4a	863
mem	lap4b	1098
mem	d4	1354
mem	lap5a	357
mem	lap5b	1491
mem	d5	1294
mem	lap6a	792
mem	lap6b	1010
mem	d6	1346

;declare registers:

equ	krt	reg0
equ	apout	reg1
equ	temp	reg4
equ	pot_one	reg5

;read-first registers:

equ	lp1	reg20
equ	lp2	reg21
equ	lp3	reg22
equ	lp4	reg23
equ	lp5	reg24
equ	lp6	reg25
equ	hp1	reg26
equ	hp2	reg27

equ	hp4	reg29
equ	hp5	reg30

;program:

;first clear read-first registers:

skp	run,endclr
wrax	lp1,0
wrax	lp2,0
wrax	lp3,0
wrax	lp4,0
wrax	lp5,0
wrax	lp6,0
wrax	hp1,0
wrax	hp2,0
wrax	hp4,0
wrax	hp5,0

endclr:

;make up krt from pot0:

rdax	pot0,1
sof	0.7,0.3
wrax	krt,0

;make up pot_one from pot1:

rdax	pot0,-1
sof	-1,0.999
wrax	pot_one,0


;calculate an address pointer for predelay:

rdax	pot2,1
and	%01111100_00000000_00000000		
sof	0.1,0		;limit to 1/10th of space
wrax	addr_ptr,0

;feed inputs to predelay:

rdax	adcl,0.25
;rdax	adcr,0.25	;leave headroom
wra	pdel,0		;write to predelay

;read predelay into ap filters:

rmpa	1

;now do reverb:

rda	ap1#,0.65
wrap	ap1,-0.65
rda	ap2#,-0.65
wrap	ap2,0.65
rda	ap3#,0.65
wrap	ap3,-0.65
rda	ap4#,0.65
wrap	ap4,-0.65
wrax	apout,0

rda	d6#,1		;read last delay output
rdax	apout,1		;read apout
mulx	krt		;scale by Krt
rda	lap1a#,0.6	;do loop all passes
wrap	lap1a,-0.6
rda	lap1b#,-0.5
wrap	lap1b,0.5
rdfx	hp1,0.05	;high pass filter (fixed)
wrhx	hp1,-0.6
wrax	temp,-1		;write to temp (for shelving LP)
rdfx	lp1,0.5		;do the LP as a HP
wrhx	lp1,-1
mulx	pot_one		;pot_one is a shelf (neg number)
rdax	temp,1		;add filter input
wra	d1,0		;write to next delay input

rda	d1#,-1
mulx	krt
rdax	apout,1
rda	lap2a#,0.6
wrap	lap2a,-0.6
rda	lap2b#,0.5
wrap	lap2b,-0.5
rdfx	hp2,0.05	
wrhx	hp2,-0.6
wrax	temp,-1
rdfx	lp2,0.5
wrhx	lp2,-1
mulx	pot_one
rdax	temp,1
wra	d2,1.9
wrax	dacl,0

rda	d2#,-1
rdax	apout,1
mulx	krt
rda	lap3a#,0.6
wrap	lap3a,-0.6
rda	lap3b#,0.5
wrap	lap3b,-0.5
wrax	temp,-1
rdfx	lp3,0.5
wrhx	lp3,-1
mulx	pot_one
rdax	temp,1
wra	d3,0

rda	d3#,-1
rdax	apout,1
mulx	krt
rda	lap4a#,0.6
wrap	lap4a,-0.6
rda	lap4b#,0.5
wrap	lap4b,-0.5
rdfx	hp4,0.05	
wrhx	hp4,-0.6
wrax	temp,-1
rdfx	lp4,0.5
wrhx	lp4,-1
mulx	pot_one
rdax	temp,1
wra	d4,0
;wrax	dacr,0

rda	d4#,-1
mulx	krt
rdax	apout,1
rda	lap5a#,0.6
wrap	lap5a,-0.6
rda	lap5b#,0.5
wrap	lap5b,-0.5
rdfx	hp5,0.05	
wrhx	hp5,-0.6
wrax	temp,-1
rdfx	lp5,0.5
wrhx	lp5,-1
mulx	pot_one
rdax	temp,1
wra	d5,1.9

rda	d5#,-1
rdax	apout,1
mulx	krt
rda	lap6a#,0.6
wrap	lap6a,-0.6
rda	lap6b#,0.5
wrap	lap6b,-0.5
wrax	temp,-1
rdfx	lp6,0.5
wrhx	lp6,-1
mulx	pot_one
rdax	temp,1
wra	d6,0

;de-ring:

skp	run,1
wlds	sin0,28,100

cho	rda,sin0,sin|reg|compc,d2+100
cho	rda,sin0,sin,d2+101
wra	d2+200,0

cho	rda,sin0,cos|reg|compc,d5+100
cho	rda,sin0,cos,d5+101
wra	d5+200,0

Is it correct way?

Posted: **Wed May 15, 2019 9:08 am**

not correct...
I've made something wrong. When I've loaded presets, I've find similar problem with both, when I turn pot0(decay) more then on 50%, effect is not decaying and become infinite high mid frequency noise. Sounds like effect looping itself and getting louder and louder until it become just loud noise.
Can you help me to solve this problem?
thanks!

Spin Semiconductor

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