I was looking to reduce the size of the previously taptempo code so i could do a clocksync'd echo with a basic reverb. This works for me for clocksync delays in a synth. IIRC it gives a saving of 12 instructions.
I've stripped out all the delay declarations, echo code etc, this is just the clocksync code.
I guess i should add that I use this for a synth module where it's usually clocked with a square wave with reasonably sharp edges. I haven't tested it with a tap tempo guitar pedal where you'd possibly need some debounce.
Code: Select all
; ***********************
; declarations
equ smooth 0.001 ; general smothing filter coeff
equ delaytime 330 ; initial delay time until we get a valid clock sync
equ holdoff_count 0.05 ; debounce counter (0.05 is 1.5msec)
equ count 0.001 ; debounce counter
; pots
equ TimePot pot0
equ overrun reg21
equ holdoff reg22
equ ramp reg23 ;current value of rmpo, scaled to 0 to 1
equ taptempo reg24 ;taptempo value, 0 to 1
;*******************************************************
; initialisation
skp run, loop
; init for clocksync
wldr rmp0, 0, 4096 ;set up rmp0
sof 0, 0.99
wrax overrun, 0 ; overrun can have any non-zero value
wrax holdoff, 0 ; clear debounce/holdoff counter
sof 0, delaytime/1000 ;set initial delay time
wrax ramp, 1
wrax taptempo, 0
; ***********************
; main loop
loop:
; get input signal
; pots
; read feedback level pot
; ***********************
; start clock sync ...
rdax TimePot, 1 ;read pot
sof 1, -0.5 ;level shift to -0.5 to 0.5
skp gez, Poz
; clock sync signal is < 0.5 (less than 1.65V at the CV input)
; just set holdoff negative
Neg:
sof 0, -count
wrax holdoff, 0
skp zro, INCLK
; clock sync signal is >= 0.5 (greater than 1.65V at the CV input)
; on the rising edge of a clock pulse ie first time through here, zero
; out the holdoff counter, it'll be negative from "Neg:"
; then increment holdoff counter
; for subequent passes just increment the holdoff counter
; when the holdoff_count passes a specific value (say, 50 == 1.5msec),
; it's safe to assume the pulse is stable so run the NEWCLK code to reset the ramp timer
; any other value just drop through to INCLK
Poz:
ldax holdoff
skp gez, Poz1 ; zero out holdoff if this is the first +ve
clr
Poz1:
sof 1, count
wrax holdoff, 1
sof 1, -holdoff_count
skp zro, NEWCLK ; clock has been +'ve for holdoff_count cycles, call NEWCLK
;tap tempo, uses rmp0 as a 1 Hz rising ramp,
; if period between clock sync pulses is greater than 1sec, overrun is 0, so just use the previous
; valid value for taptempo
INCLK:
ldax overrun
skp zro, END_CLKSYNC ; overrun is 0 if this cycle has overrun
sof 0, 0.0625
wrax rmp0_rate, 0 ;set rmp0 rate to 1Hz
cho rdal, rmp0 ;read value of rmp0
sof -2, 0.999
sof 1, 0.001 ;level shift to 0 to 1 rising ramp
wrax ramp, 1 ;write to ramp
sof 1, -0.999 ;deduct 1 from ramp (use 0.5 for dual tap delay)
skp neg, END_CLKSYNC ;if answer is positive then second tap hasn't happened with 1s of first
OVER_RUN: ; timer has overrun 1sec, so ignore this sample period, use previous legit one
ldax taptempo ;so keep last value of taptempo
wrax ramp, 0
wrax overrun, 0 ; overrun is 0 this clock cycle has overrun
skp zro, END_CLKSYNC ;jump to end of clocksync
; this code is run at the start of a new clock pulse
; reset rmp0 & read the previous ramp count into taptempo
NEWCLK:
jam rmp0
ldax ramp
wrax taptempo, 1
wrax overrun, 0 ; stuff any non-zero value into overrun
END_CLKSYNC:
; ***********************
ldax taptempo
rdfx offset, smooth
wrax offset, 0
; ***********************
;; either ...
;ldax taptempo
;rdfx offset, smooth
;wrax offset, 0
;; delay tap
;or DelayMem * 256
;rdax offset, 1
;wrax addr_ptr, 0
;rmpa 1
; ***********************
;; or if you're really short on instructions & need 2 more, replace the last bit with
clr
or DelayMem * 256
rdax taptempo, 1
wrax addr_ptr, 0
rmpa 1
; rest of code here ...